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SRC4392 output zero's

Other Parts Discussed in Thread: SRC4392, SRC4192

Hi,

I'd like to use the SRC4392 chip to output a muted digital signal when it isn't receiving one and to output the signal it receives when it is receiving one.  I think i have second part working, i'm just not sure how to get the muting part to work.

I'm using the SRC-4392 evaluation board for testing and below is my current registration commands using the bundled software.  Some of the comments might be incorrect from just tinkering with the various options.  Any help would be greatly appreciated.

Cheers,
Chris

# sample SPI script
# set interface mode to spi 16 bit address
i spi16
w 01 00 80
# set register page to 0
w 7f 00 00
#0b00111001 // SRC PortA Master, I2S, SRC
w 03 00 35
#0b00000000	// SRC PortA MCLK /128 (24.576/128=192k)
w 04 00 00
# 05 was changed from 01 to 21
#0b00000001	// SRC PortB Master Input, I2S
w 05 00 01
#0b00000000	// SRC PortB 
w 06 00 00
# 0d was 08, changed to 00 RXCLK
#0b00001000	// SRC Digital Interface Receiver: MCLK, RX1
w 0d 00 00
#0b00001000	// SRC DIR: LOL, Auto-Mute, PLL/1, No RXCKO
w 0e 00 10
#0b00000100	// SRC DIR Interrupt Mask1: DIR INT, MUNLOCK
w 16 00 04
#0b00000000	// SRC DIR Interrupt Mask2: default
w 17 00 00
#0b00000000	// SRC DIR Interrupt Mode1: default DIR INT rising edge
w 18 00 00
#0b00100010	// SRC DIR PLL1 reg 1: 24.576MHz
w 0f 00 22
#0b00000000	// SRC DIR PLL1 reg 2:
w 10 00 00
#0b00000000	// SRC DIR PLL1 reg 3:
w 11 00 00
#0b00010010	// SRC,MCLK,DIR,MUTE
w 2d 00 12
#0b00000000
w 2e 00 00
#0b00010000	// SRC INT, MREADY
w 0b 00 10
#0b00000000	// interrupt mode
w 0c 00 00
#changed from f8 to 78
#0b01101000	// DIT MCLK, /512, PortB (for USB only)
w 07 00 78
#changed from 94 to 14
#0b10010100	// DIT BYPMUX_RX3, LDMUX, NO_AES, TX_ON
w 08 00 34	//changed to 14, RX1 instead of RX3
#0b00000000
w 09 00 00
#0b00000000	// Output Low, RLY1
w 1b 00 00
#0b00000000	// Output Low, RLY2
w 1c 00 00
#0b00000110	// Non-Audio DATA
w 1d 00 06
#0b00000111	// Non-Valid DATA
w 1e 00 07
#0b00111111	// Power-Up PortA, PortB, TX, DIR, SRC
w 01 00 3f

  • Hi Chris,

    From the looks of your code, you are imputing a signal into the DIR, and when you are not receiving a signal you want the output muted, is this a correct understanding of your goal?

    If not could you please clarify what is it you want to do with what ports? A schematic of connections could help.

    The only IP in the SRC4192 that will automatically mute with loss of signal is the DIR, and this is done by setting the RXMLL bit in register 0E. This will make the DIR mute itself if it loses lock on the input signal. All other mutes done in software are manual mutes taht must be set by a host controller. This is why we have the LOCK, RDY, and MUTE pins. if lock is lost in the DIR, then the lock pin will change, this signal can be connected to the MUTE pin for an automatic mute all outputs, not just the DIR output.

    Justin
  • Hi Justin,

    Thanks for the fast reply.

    My goal is to always be feeding my dac a signal to avoid pop's created when it stops receiving and then starts to receiving spdif signal. I figured if I placed an SRC4392 chip between the output device and the dac and told it to output zero's when ever it wasn't receiving signal this might help. I changed register 0e to 08, but my dac isn't receiving a lock, are there other values that need to be changed?

    Cheers,
    Chris
  • I managed to get Port B to continue outputting a clock signal even when not receiving signal by setting it to master 0b00101001 (reg 05). Any way to get this to TX1?