Hi,
I'm working on aci23 with c2811, first i'm trying to make tx(2811->aic23) path correct , so i generated a single tone inside 2811 and output it to aic23 through mcbsp, but i can not get correct waveform by scope.
I want aic23 working on normal mode with a 12.88MHz crystal outside, and adc and dac working on 8kHz sample rate. Here is the aic23 config code section:
// RESET(7'b000 1111): 9'b0 0000 0000
// RES(D8:D0)=0: trigger reset
WriteCodecReg(0x1a, 0x1e, 0x00);
// POWER_CON(7'b000 0110): 9'b0 0000 0000)
// OFF(D7)=0: device power on
// CLK(D6)=0: clock on
// OSC(D5)=0: oscillator on
// OUT(D4)=0: outputs on
// DAC(D3)=0: DAC on
// ADC(D2)=0: ADC on
// MIC(D1)=0: mic input on
// LINC(D0)=0: line input on
WriteCodecReg(0x1a, 0x0c, 0x00);
// A_AUDIO_PATH(7'b000 0100): 9'b0 0001 0000
// STA(D7:D6)=2'b00: sidetone attenuation=6dB
// STE(D5)=0: sidetone disable
// DAC(D4)=1: DAC enable
// BYP(D3)=0: bypass mode disable
// INSEL(D2)=0: ADC input select Line
// MICM(D1)=0: mic not muted
// MICB(D0)=0: mic boost=0dB
WriteCodecReg(0x1a, 0x08, 0x10);
// D_AUDIO_PATH(7'b000 0101): 9'b0 0000 0000
// DACM(D3)=0: DAC soft mute disable
// DEEMP(D2:D1)=2'b00: de-demphasis control disable
// ADCHP(D0)=0: ADC high-pass filter disable
WriteCodecReg(0x1a, 0x0a, 0x01); // 0x00
// D_AUDIO_INTERFACE(7'b000 0111): 9'b0 0100 0011
// MS(D6)=1: master mode
// LRSWAP(D5)=0: DAC left/right swap disable
// LRP(D4)=0: for dsp mode: MSB is 1st bclk after LRCIN
// IWL(D3:D2)=2'b00: input bit length=16
// FOR(D1:D0)=2'b11: data format = DSP format
WriteCodecReg(0x1a, 0x0e, 0x43);
// SAMPLE_RATE(7'b000 1000): 9'b0 0000 1100
// CLKIN(D6)=0: clock input = MCLK
// CLKOUT(D7)=0: clock output = MCLK
// SR[3:0](D5:D2)=4'b0011: sample rate = 8k
// BOSR(D1)=0, sample rate = 8k
// USB/Normal(D0)=0: clock mode = normal
WriteCodecReg(0x1a, 0x10, 0x0c);
// D_INTERFACE_ACT(7'b000 1001): 9'b0 0000 0001
// ACT(D0)=1: activate interface
WriteCodecReg(0x1a, 0x12, 0x01);
// L_LINE_VOLUME(7'b000 0000): 9'b1 0001 1011
// LRS=1(D8): left/right simultaneours update
// LIM=0(D7): normal, not muted
// LIV(D4:D0)=5'b11111:12dB // 5'b10111(D4:D0): 0dB
WriteCodecReg(0x1a, 0x01, 0x1B);
// R_LINE_VOLUME(7'b000 0001): same as above
// WriteCodecReg(0x1a, 0x03, 0x1B);
// L_HDPHONE_VOLUME(7'b000 0010): 9'b1 1111 1001
// LRS(D8)=1: left/right simultaneours update
// LZC(D7)=1: zero cross dectect on
// LHV=7'b1111001: 0dB
WriteCodecReg(0x1a, 0x05, 0x70); // 0x79); // 0xf9);
// R_HDPHONE_VOLUME(7'b000 0011): 9'b1 1111 1001
// WriteCodecReg(0x1a, 0x07, 0x70); // 0xf9);
And i'm sure aic23 config interface should be working correctly ,since i tried the bypass and sidetone way of aic23, and they both work fine. Belowing is my mcbsp configuration for audio data transfer:
McbspaRegs.SPCR2.all = 0x0000;
McbspaRegs.SPCR1.all = 0x0000;
McbspaRegs.SPCR1.bit.DLB = 0; // disable loopback mode
McbspaRegs.SPCR1.bit.RJUST = 0; // right-justify and zero-fill MSB
McbspaRegs.SPCR1.bit.CLKSTP = 0; // for clock stop mode, no use
McbspaRegs.SPCR1.bit.DXENA = 0; // DX enabler off
McbspaRegs.SPCR1.bit.ABIS = 0; // A-bis mode disable
McbspaRegs.SPCR1.bit.RINTM = 0; // RRDY->RINT
McbspaRegs.SPCR1.bit.RRST = 0; // rx reset
McbspaRegs.SPCR2.bit.FREE = 1; // bit 9: free running mode enable
McbspaRegs.SPCR2.bit.SOFT = 0; // bit 8: soft mode disable
McbspaRegs.SPCR2.bit.FRST = 0; // bit 7: frame sync logic is reset
McbspaRegs.SPCR2.bit.GRST = 0; // bit 6: sample rate generator is reset
McbspaRegs.SPCR2.bit.XINTM = 0; // bit 5-4: XRDY->XINT
McbspaRegs.SPCR2.bit.XRST = 0; // tx reset
McbspaRegs.MFFTX.all = 0x4024; // 0x4028; // transmit 12 data every int
McbspaRegs.MFFRX.all = 0x002C; // 0x0028; // receive 12 data every int
McbspaRegs.MFFCT.all=0x0000;
McbspaRegs.MFFINT.all=0x0000;
McbspaRegs.MFFST.all=0x000;
McbspaRegs.MFFTX.bit.TXFIFO_RESET=1;
McbspaRegs.MFFRX.bit.RXFIFO_RESET=1;
McbspaRegs.RCR2.bit.RPHASE = 0; // bit 15: single phase frame
McbspaRegs.RCR2.bit.RFRLEN2 = 0; // bit 14-8: 1 word/frame for phase 2
McbspaRegs.RCR2.bit.RWDLEN2 = 2; // bit 7-5: 16 bits
McbspaRegs.RCR2.bit.RCOMPAND = 0; // bit 4-3: no companding, msb first
McbspaRegs.RCR2.bit.RDATDLY = 0; // bit 1-0: 0-bit data delay
McbspaRegs.RCR1.bit.RFRLEN1 = 1; // 0; // bit 14-8: 1 word/frame for phase 1
McbspaRegs.RCR1.bit.RWDLEN1 = 2; // bit 7-5: 16 bits
McbspaRegs.XCR2.bit.XPHASE = 0; // bit 15 : single phase frame
McbspaRegs.XCR2.bit.XFRLEN2 = 0; // bit 14-8: 1 word/frame for phase 2
McbspaRegs.XCR2.bit.XWDLEN2 = 2; // bit 7-5: 16 bits
McbspaRegs.XCR2.bit.XCOMPAND = 0; // bit 4-3: no companding, msb first
McbspaRegs.XCR2.bit.XDATDLY = 0; // bit 1-0: 0-bit delay
McbspaRegs.XCR1.bit.XFRLEN1 = 0; // bit 14-8: 1 word/frame for phase 1
McbspaRegs.XCR1.bit.XWDLEN1 = 2; // bit 7-5: 16 bits
McbspaRegs.PCR.all = 0x03; // CLKRP=1: rcv data sampled at rising edge
// CLKXP=1: tx data sampled at falling edge
McbspaRegs.PCR.bit.FSXM = 0; // bit 11: fsx driven by external source
McbspaRegs.PCR.bit.FSRM = 0; // bit 10: fsr driven by external source
McbspaRegs.PCR.bit.CLKXM = 0; // bit 9: clkx driven by external source
McbspaRegs.PCR.bit.CLKRM = 0; // bit 8: clkr driven by external source
McbspaRegs.PCR.bit.CLKXP = 1; // bit 1: tx data sampled on falling edge
McbspaRegs.PCR.bit.CLKRP = 1; // bit 0: rx data sampled on rising edge
NOP;
NOP;
McbspaRegs.DXR1.all = 0;
McbspaRegs.SPCR1.bit.RRST = 1;
McbspaRegs.SPCR2.bit.XRST = 1;
NOP;
NOP;
Anybody can help me out?
thanks,
Weslly
