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PCM17*** audio dacs - BCK specifications

Other Parts Discussed in Thread: PCM1754

I am looking for a DAC to replace a Wolfson WM8727, and I don't find the spec for the BCK signal to be very clear.

On the Wolfson part these is little restrictions on BCK timing, provided that the correct number of BCK clocks appear between edges of LRCLK, so I have been using the SPI port of a microcontroller to send audio data.

It seems from the TI data sheets that BCK must be a constant speed and tied to MCLK in some way. Is this correct?

  • Hi Ian,

    BCK and MCLK are kind of indirectly related. The main relationship stems from those two clocks and LRCLK.

    BCK = LRCLK * # of channels * word size
    The bit clock is used for the data processing.

    MCLK is typically going to be much faster than the BCK, but is still related to the LRCLK. MCLK is generally a factor of 2^n * LRCLK. For example, in a lot of devices you at least of the option of a MCLK being 256 * LRCLK = 2^8 *MCLK or MCLK = 128*LRCLK = 2^7 * LRCLK.

    I hope this answers your question.

    As for an alternative to the WM8727, I would recommend the PCM1754 unless you are looking for more features from your DAC. If you are, let me know what features you would like and I can see if we have a device that does what you want.

    Regards,
    Mike Ulrich
  • Thanks.
    I've already got MCLK at 11.289MHz (from the CPU's CLOCKOUT) and LRCLK at 44.1kHz (using one of its timers to divide by 256).
    I wasn't sure if BCLK had to be a fixed speed, or I could just use the SPI port's CLK signal (which I did for the WM8727) - this leads to two bursts of 13 clocks with a gap between them and then a space until LRCLK changes state. The WM8727 is quite happy with that, but a Cirrus CS4334 wasn't. I was just wondering which one the PCM1754 would behave like.
  • A reply would be appreciated
  • Hi Ian,

    While they do not have to be in phase, MCLK and BCK must be synchronous. Along with that, many of the PCM17XX DACs give a figure that shows the relationship between LRCK, BCK, and data. With this figure and the understanding that BCK and LRCK must be synchronous with MCLK, this provides the needed information.

    Justin