Dear TI expert,
I am testing the PCM1865 for an application where there will be rapid changes in the sampling frequency. I try to use such a configuration where the PLL is off. This is in order to avoid PLL locking delays, and also my Fs range is slightly larger than the PLL locking range. The data sheet Table 10 suggests that shutting the PLL off is possible for SCK ratios from 512 to 768, and such ratios seem to be working indeed in my prototype. My preferred SCK ratio, however, would be 256, but when I use it, Dout signal disappears. Is there any way to make it work which such a ratio?
This is not very critical, because I can change my circuitry to higher external clock and then use a higher ratio. However, more important is to know if the ADCs work when I vary the sampling frequency within a range of 1 to 2 by a corresponding variation in the input external clock? I guess if the PLL is completely inactive, there would be no problems, but my concern is on the sentence on the data sheet page 34 that says "The PLL by default is enabled because the on-chip fixed function DSPs require high clock rates to complete all various decimation, mixing and level-detection functions". So, even when I disable PLL, is it still used internally? I do not yet have my prototype programmed to test and try what happens when varying the external clock.
Best Regards,
Jouko
