• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 30 subscribers
  • Views 9001 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

I2S Multi-Slave / Multi-Master configurations

_Lina
Expert 3305 points
Other Parts Discussed in Thread: TLV320AIC3254

Hi Team,

In a system with three devices, lets say a CODEC, Audio DSP (C55x) and another processor, if the processor is the I2S master device, can the DSP and CODEC communicate independently of the ARM9, assuming they are slaves? In other words, how would the communication take place between the DSP and the CODEC assuming that the processor is the master? 

I am familiar with I2C, SPI and other comm. topologies but not so much I2S. In the case of I2C and SPI, I know that the communication is controlled by the master...so such configuration would not be possible unless routed through the master. Is the same true for I2S?

Assuming this is not possible and there will be multiple master devices, what steps must be taken to mitigate synchronization issues if trying to mix audio data from both masters in one slave for example?

Thanks in advance,

  • 0
    TI__Guru* 84915 points

    Hi _Lina,

    I suggest to take a look of this document: Audio Serial Interface Configurations for Audio Codecs. It could help you to understand about the I2S behavior as a master and as a slave.

    Regarding your question about the communication between slaves, when a device is working as slave, the BCLK and WCLK are placed as inputs. So, the communication can't take place between them because both devices would wait for the master clocks.

    It is not recommended to use multiple masters with an I2S protocol. Could you provide more information about the communication between slaves?

    There're many codecs (such the TLV320AIC3254) that have a miniDSP included. You may take a look of the TLV320AIC3254 datasheet if you're interested in the miniDSP.

    I hope this helps you. If you still have questions, please let me know.

    Best regards,

    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Expert 3305 points

    Hi Luis,

    Thanks for your response!

    I did see that document but still having trouble understanding how communication takes place, especially with an external clock controller with all of the devices as slaves.

    To answer your question regarding slave to slave comms, this is what is needed in the system:

    1. The codec needs to send i2s data to the C5000 DSP for processing

    2. The DSP needs to send i2s data to the other processor.

    3. The processor needs to receive i2s data from the CODEC.

    Which configuration of master/slave would you use to achieve this design?

  • 0 in reply to _Lina
    TI__Guru* 84915 points

    Hi _Lina,

    If my understanding is correct, the system can be described as the following picture shows:

    The I2S protocol is based in four lines: BCLK, WCLK, DIN and DOUT. The master determines the BCLK and WCLK frequency, so both  lines must be configured as outputs in order to use a device as a master. For this system, if the processor is able to generate both clocks, it would be the master. The DSP and the CODEC could be configured as slaves (BCLK and WCLK as inputs).

    However, the DSP and Processor would work with two different lines of data as the diagram shows. In this case, the DSP and the Processor would need two I2S interfaces in order to use the two lines of different data. The Codec would need one I2S interface because it would work with one line.

    I hope this helps you. If you still have questions, please let me know.

    Best regards, 

    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Expert 3305 points

    Hi Luis,

    This is all great info, thanks!

    The diagram actually looks like the below (I forgot to mention one more communication line between processor feeding into the DSP):

    Each device has enough I2S channels to achieve this design.

    My question is more along the lines of how the data takes place between the CODEC_DOUT2 to DSP_DIN1. If the Processor generates the clocks, it should still be ok right?

    Thanks for your help!

  • 0 in reply to _Lina
    TI__Guru* 84915 points

    Hi _Lina,

    Thank you for provide an additional diagram.

    There should be no problem as long as the processor works as the master and the codec and DSP as the slaves. All the devices would work at the same frequency, so both slaves (DSP and codec) would be synchronized. The data would be transmitted correctly between them.

    I hope this helps you. If you still have questions, please let me know.

    Best regards,

    Luis Fernando Rodríguez S.