TLV320AIC3110 - Master I2S configuration

Leonardo Garberoglio

Hi, I have an evaluation board with this codec and I'm trying to configure the codec to generate all Clock pulses (BCLK, WCLK, MCLK). i already disable TAS1020b I2S interfaz, but I can't obtain pulses coming out of the codec...

over 10 years ago

0 Dominik Hartl11 over 10 years ago

TI__Guru 62006 points

You need to supply either MCLK or BCLK (if you use the PLL) externally. The codec needs an external clock (typically MCLK) to generate the audio clocks.

0 Leonardo Garberoglio over 10 years ago in reply to Dominik Hartl11

Intellectual 420 points

I see, and how acurate the MCLK should be? I'm looking at the table 5.42 and for 44.1KHz I could have a PLL input of 12MHz. My uC provide this clock, but how acurate should be?

Than for your answer!

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TLV320AIC3110 - Master I2S configuration