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How does PCM1808 slave mode know what rate to sample the input at?

curiousengineer
Prodigy 40 points
Other Parts Discussed in Thread: PCM1808

The datasheet of PCM1808 contains table 1 found here on page 11. It lists the possible sampling rates as 8, 16, 32, 44.1, 48, 64, 88.2, 96 KHz. It then lists the master clock values required for these different sampling rates. If we look at it e.g 16.384MHz master clock can give 32KHz sampling frequency (512 fs) or 64KHz sampling frequency (256 fs). It then says that "The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode" .

I have the following questions:

Precisely what determines the sampling rate of the PCM1808 in slave mode? Why are there only such discrete values?

If I connect a 16.384MHz crystal as master clock source for the PIC microcontroller as the master and PCM1808 as the slave, how will the PCM1808 know what rate to sample the input signal i.e 32KHz or 64KHz?

When does the PCM1808 sample an input signal, is it when the LRCK is asserted or is sampling the input signal contiously? i.e if I read the ADC at time T, which sample in time of the input signal am I reading?

At what rate can one read the data from the ADC? e.g if sampling rate is 44KHz, does the PIC need to leave everything else and just read the ADC and this rate? Can the ADC use timer interrupts for this purpose?

 

  • 0
    TI__Mastermind 27990 points
    Hi,

    The PCM1808 is meant for Audio applications and uses the I2S interface. The I2S interface uses a data line, BCK (bit clock), LRCK (left right clock), and SCK (system clock). The BCK determines the rate at which the bits will be transferred and how many bits per LRCK. In master mode BCK will be 64*Fs or 64 bits per sample/ 32 bits per channel. In Slave mode, BCK can be either 64*Fs or 48*Fs.

    When operating an SCK must be provided to the PCM1808 for normal operation. In Slave mode, BCK and LRCK must also be sent to the PCM1808 from the master. When receiving SCK, BCK, and LRCK, a comparison of those three clocks can give you the ratio in question, this is what the internal circuitry of the PCM1808 does. The clocks given are clocks used for common audio sampling rates. If you use a nonstandard SCK, the resulting sampling rate will not be a standard audio sampling rate.

    In master mode the LRCK and BCK output is manually selected by pins of the part (MD1 and MD0).

    These clocks

    Since this part is meant for audio, the ADC will sample the analog input at a high rate and decimate the content to the sampling rate, determined by LRCK. Holding LRCK high or low will not provide continuous samples, it will halt the output.

    2 samples (left and right) will be provided every period of LRCK, left in the first half (high) of the LRCK period, one in the second half (low) of the LRCK period.

    Justin