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IADC / IDAC Vs DSP_A DSP_D cycles and clock scheme

LostElectron
Prodigy 180 points

Hello,

One important thing to understand and to setup when are going to used 32XX families for the first time is

how to get a correct clock scheme for the device.

I think there is a lack of description on the relationship (when miniDSP's are planned to be used) between clocks setup and miniDSP cycles...

Can someone explain or point me out on a document if there is one on the relationship between IDAC/IADC setup and DSP_A DSP_D cycles.

My first DSP trials (just a DIN/DOUT digital loopback) fails to run and it takes me a while before to understand that my DSP cycles i.e 904 (default 3254_8x4 framework values when you dump the block on your scheme) were greater than the acceptable values for my design and my actual clock setup.

The clock setup and pll setup is widely documented on the 3254 spec but there absolutely nothing about  the relationship with miniDSP's capabilities.

If there is a document explaining this so far  it must referenced in clock setup section of the main 3254 specification. IADC and IDAC are undefined acronyms ...

Let me know.  Thanks.

  • 0
    TI__Guru* 84915 points

    Hi,

    We will check this and we will answer you as soon as possible.

    Thank you.

    Best regards,

    Luis Fernando Rodríguez S.

  • 0
    TI__Mastermind 46195 points
    Hi,

    You're right. The AIC3254 datasheet lacks depth regarding IDAC and IADC information. The configuration for these registers is handled automatically by PurePath Studio based on the framework you select.

    If your design closely follows the clocking setup of the EVM , then minor changes are needed. However, if you clocking is different, you would need to modify the clock tree and PLL as you mentioned. Information about IDAC and IADC can be found in this wiki page: e2e.ti.com/.../1098.aic3254-minidsp-d-cycles-and-minidsp-a-cycles

    Note that cycles = 904 is fine for 48k sampling as long as the max miniDSP_CLK restriction in the datasheet is satisfied. The miniDSP_CLK is basically DAC_FS*IDAC and ADC_FS*IADC. IDAC and IADC are the values you specify in PPS.

    Regards,
    J-
  • 0 in reply to J-
    Prodigy 180 points

    My design workflow was at the opposite. I have setup the EVM (using external MCLK input) to match the design. And the target is voice application so using 8K sampling.

    Anyway this was helpful. Thank you.

  • 0 in reply to LostElectron
    Prodigy 180 points

    One additional question...

    I am going to use the base_main_Rate8.cfg file to load my design over the i2c link.

    That's fine.

    Now I just realized since I am using more cycles than initially though, the file size has increased significantly - and my setup will also be longer in time -.

    This increase is big enough to make me think on reducing the number of cycles to use to the exact required number of cycles to be able to perform the function seamlessly.

    Before doing that I would like to understand if there any advantages in having more cycles that the necessary ones.

    I observed that more you allocate more the tool will spend... 

    I am running a Voice-operated switch algorythm for both left and right separately and I am afraid of some faults, or latencies if the case where cycles are restricted to the minimum... 

    Can you give me some advices on that ?

  • 0 in reply to LostElectron
    TI__Mastermind 46195 points

    Hi,

    Changing cycles does not affect algorithm behavior or latency. Here are the settings I recommend:

    1. Keep the ratio between miniDSP_D cycles and miniDSP_A cycles between 0.5 and 2 if passing data between processors. If not passing data between processors, this doesn't matter.

    2. Do not use sync mode (this requires specific settings and complicates things).

    Regards,

    J-