• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 544 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

When is SPK_GAIN/FREQ sampled?

Eric Raquette
Intellectual 260 points
Other Parts Discussed in Thread: TAS5754M, TAS5756M

I have a TAS5754M board and don't get the expected gain and frequency.

I have 75k and 470k resistors connected from GVDD to GND that should result in 26dB and 8xFsync but I only get 20dB gain.

Maybe be chip is reading the voltage while GVDD is still rising and I also see only 5.5V on GVDD until clocks are configured (master mode).

GVDD then becomes 6.8V.

Can a trigger a new reading by writing to register P0-R1 or P0-R2?

  • 0
    TI__Mastermind 34775 points

    Hi Eric,

    Are you using our EVM? This is strange. Do you have scope captures of your PVDD and GVDD during power up? I don't think it's the detection of the SPK_GAIN/FREQ pin, since it's ratiometric to GVDD.

     

  • 0 in reply to Damian Lewis
    Intellectual 260 points

    Hi Damian

    I have checked on the EVM and on our custom board. I see +20dB gain from pin SPK_INA+ to output after filter.
    So I now think this is another datasheet error, table 15 is not correct. The EVM PCB has silk screen with the correct gain/freq that I didn't see before.
    The answer that the setting is ratiometric to GVDD and not absolute like table 15 is important to my understanding of the pin.

    The scope picture was posted in the "TAS5756M question on switching frequency" thread that you replied to last week,
    (I think my question was relevant in that thread since it was related to the original question).
    Your answer there: "To see the gain and switching frequency change, state of the SPK_GAIN/FREQ pin must be set prior to powering up the device. The device has to be powered down and powered up for the gain and/or frequency change to take effect." is still not clear to me.
    Can the power cycle be done via P0-R1/R2 or only externaly?

    Eric

  • 0 in reply to Eric Raquette
    TI__Mastermind 34775 points

    Hi Eric,

    Sorry I don't recall your previous post. Can you provide a reference to the post? I assuming you're expecting 768kHz switching rate and 26dBV at the output. Which is correct for the resistor divider ratio you selected. The SPK_GAIN/FREQ pin sets the output stage gain to 16 or 20dB a shown on the EVM, but the system gain changes to 20 or 26dB as stated in the d/s due to the 6dB internal DAC gain that must be accounted for. The table 15 is a guide for GVDD = 7V. Which is the most typical case where PVDD > 8V. It has to be ratiometric else it would work for case where PVDD < 8V, for example 5V because at PVDD = 5V GVDD ~4.5V.

    The device has to be PVDD power cycled for changes in the SPK_GAIN/FREQ pin to take effect. It can't be down via register P0-R2/R1.