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Need basic register settings for TLV320AIC3101 when BCLK is acting as MCLK

Other Parts Discussed in Thread: TLV320AIC3101

Hi,

In one of my project I am interfacing my TLC320AIC3101 with Atmel SAM3x for recording the voice received from mic. I have interfaced the BCLK,WCLK,DOUT and DIN to the i2s lines of SAM3x controller at TK,TF,RD and TD respectively. There is no MCLK as I want to use BCLK as MCLK as mentioned in TLV320AIC3101 datasheet as "CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7–D6." or "PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5–D4". I have connected the i2c lines of TLV320AIC3101 to my SAM3x i2c where SAM3x i2c is acting as i2c Master.

I am successfully able to read and write the registers of TLV320AIC3101 using my SAM3x i2c Master driver. Now I want to know which registers I can set so that when I speak through the mic and I get the voice in i2s or loopback to headphone and also how do I test the headphone by playing a sinewave on i2s?

Which mode should I use CLKDIV_IN mode or PLL mode?

Here is the code I am trying but don't know why it is not working

/* Configure AIC3101 */
    i2c_write(  0, 0 );            // Page select register -> Page 0
    i2c_write(  1, 0x80 );         // Reset AIC3101
 
     /* Configure AIC3101 registers */

   	data = i2c_read(3); // just to see if i2c is working

       i2c_write(  7, 0x0A );  // 7 Codec Datapath Setup             <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT]
	i2c_write(  9, 0x00 );  // 9  Audio Interface Control B       <- [I2S mode][16 bit]
	i2c_write(  15, 0 );    // 15  Left ADC PGA Gain              <- [Mute=OFF]
   	i2c_write(  16, 0 );    // 16 Right ADC PGA Gain              <- [Mute=OFF]
   	i2c_write(  19, 0x04 ); // 19  LINE1L to  Left ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
   	i2c_write(  22, 0x04 ); // 22  LINE1R to Right ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
   	i2c_write(  27, 0 );    // 27  Left AGC B                     <- [OFF]
   	i2c_write(  30, 0 );    // 30 Right AGC B                     <- [OFF]
   	i2c_write(  37, 0xE0 ); // 37 DAC Power & Output Dvr          <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
   	i2c_write(  38, 0x10 ); // 38 High Power Output Dvr           <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
    i2c_write(  43, 0 );    // 43  Left DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
  	i2c_write(  44, 0 );    // 44 Right DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
   	i2c_write(  47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume         <- [Routed]
   	i2c_write(  51, 0x09 ); // 51           HPLOUT Output         <- [Mute=OFF][Power=ON]
   	i2c_write(  58, 0 );    // 58           HPLCOM Output         <- []
   	i2c_write(  64, 0x80 ); // 64 DAC_R1 to HPROUT Volume         <- [Routed]
   	i2c_write(  65, 0x09 ); // 65           HPROUT Output         <- [Mute=OFF][Power=ON]
   	i2c_write(  72, 0 );    // 72           HPRCOM Output         <- []
    i2c_write(  82, 0 );    // 82 DAC_L1 to LEFT_LOP/M Volume     <- []
    i2c_write(  86, 0 );    // 86           LEFT_LOP/M Output     <- []
    i2c_write(  92, 0 );    // 92 DAC_R1 to RIGHT_LOP/M Volume    <- []
    i2c_write(  93, 0 );    // 93           RIGHT_LOP/M Output    <- []
    i2c_write( 101, 0x00 ); // 101 GPIO Control Register B        <- [CODEC_CLKIN = PLLDIV_OUT]
	i2c_write( 102, 0xA2 );    // 102 Clock Generation Control       <- [PLLCLK_IN and CLKDIV_IN use BCLK]

    data =0x00;
	data = i2c_read(14);
	if(data&0x10)
	{
		printf("\nHeadset Detected");
	}
    /* Play Tone */
    for ( sec = 0 ; sec < 10 ; sec++ )
    {
        for ( msec = 0 ; msec < 1000 ; msec++ )
        {
            for ( sample = 0 ; sample < 48 ; sample++ )
            {
               
	         	i2s_write(sinetable[sample]);

              
            }
        }
    }

    /* Close Codec */ 
    i2c_write( 0, 0 );      // Page select register -> Page 0
    i2c_write( 1, 0x80 );   // Reset the AIC3101
    

Can someone please help me in making it work? I have the EVM development kit and arduino due board.I am using Atmel Studio with ASF for my development. The EVM software does not work on my windows 8 machine. So can experiment on that.

  • Hi Anand,

    Welcome to E2E and thank you for your interest in our products.

    Regarding your question about the CLKDIV_IN and PLL mode, it depends the frequency of your MCLK (in this case, you BCLK). You only need to reach the sampling rate using CLKDIV_IN or PLL mode.  For typical sampling rates, fs(ref) is either 44.1kHz or 48kHz. I suggest to try to configure the CLKDIV_IN mode first (as 11.3.3.1 Audio Clock Generation section mentions). If it is not possible to obtain 44.1kHz or 48KHz with this mode, you will need to change to PLL mode. The device can accept a MCLK input from 512kHz to 50MHz.

    Once the clock is configured properly, it should work if the i2s protocol is respected.

    I hope this helps you. If you still have questions, please let me know.

    Best regards,

    Luis Fernando Rodríguez S.