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PCM3070 Codec Data Interface

Ignasi Pascual de Labasti
Intellectual 850 points
Other Parts Discussed in Thread: PCM3070

Hello all,

I'm using the pcm3070 in a evaluation board evmc5517. Using the code examples, I made work the classic function on getting the input, ADC, data to host via I2S bus, then, sent it back with I2S to Codec to DAC.

I wanted to modify the registers and the configurations of the PCM3070, so data is shortcutted, so from in ->adc->dac-> output, but I couldn't succed. All data are transfered throught i2s.

After reading the documentation, application note, I couldn't find the proper register that allow me to have the main processing chain inside the pcm3070. Could you help me? By the way, unsuccesfully tried PurePath, with no better results.

Thank you in advance

ip

  • 0
    Intellectual 850 points

    Hello all,

    I still couldn't succeed. I cannot find a way to use PCM3070 without using I2S, just making the signal flow throught in->adc->dac->output. Any examples or help?

    In case it helps, here the code I'm using right now. With BCLK and WCLK (register 27 ) as outputs, and a loop on the data interface (register 29 ). I hope you can help me to find why it's not working

     /* Configure AIC3204. Code used on PCM3070 . Function AIC3204_rset(Address Register, Data Register) set the registers on the PCM3070 */

	    AIC3204_rset(  0, 0x00 );      // Select page 0
	    AIC3204_rset(  1, 0x01 );      // Reset codec
	    AIC3204_rset(  0, 0x01 );      // Point to page 1
	    AIC3204_rset(  1, 0x08 );      // Disable crude AVDD generation from DVDD
	    AIC3204_rset(  2, 0x00 );      // Enable Analog Blocks

	    /* PLL and Clocks config and Power Up */
	    AIC3204_rset(  0, 0x00 );      // Select page 0
	    AIC3204_rset( 27, 0x0C );      //  BCLK and WCLK as output.
	    AIC3204_rset( 29, 0x10 );	   /// Loop on the ADC to DAC

	 
	    AIC3204_rset(  4, 0x00 );      // PLL setting: PLLCLK <- MCLK and CODEC_CLKIN <- MCLK
	    AIC3204_rset(  6, 0x20 );      // PLL setting: J=32
	    AIC3204_rset(  7, 0 );         // PLL setting: HI_BYTE(D = 0)
	    AIC3204_rset(  8, 0 );         // PLL setting: LO_BYTE(D) = 0

	    /* For 48 KHz sampling */
	    AIC3204_rset(  5, 0x92 );      // PLL setting: Power up PLL, P=1 and R=2
	    AIC3204_rset( 13, 0x00 );      // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
	    AIC3204_rset( 14, 0x80 );      // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
	    AIC3204_rset( 20, 0x80 );      // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
	    AIC3204_rset( 11, 0x88 );      // Power up NDAC and set NDAC value to 8
	    AIC3204_rset( 12, 0x82 );      // Power up MDAC and set MDAC value to 2
	    AIC3204_rset( 18, 0x88 );      // Power up NADC and set NADC value to 8
	    AIC3204_rset( 19, 0x82 );      // Power up MADC and set MADC value to 2

	    /* DAC ROUTING and Power Up */
	    AIC3204_rset(  0, 0x01 );      // Select page 1
	    AIC3204_rset( 12, 0x08 );      // LDAC AFIR routed to HPL
	    AIC3204_rset( 13, 0x08 );      // RDAC AFIR routed to HPR
	    AIC3204_rset(  0, 0x00 );      // Select page 0
	    AIC3204_rset( 64, 0x02 );      // Left vol=right vol
	    AIC3204_rset( 65, 0x00 );      // Left DAC gain to 0dB VOL; Right tracks Left
	    AIC3204_rset( 63, 0xd4 );      // Power up left,right data paths and set channel
	    AIC3204_rset(  0, 0x01 );      // Select page 1
	    AIC3204_rset( 16, 0x06 );      // Unmute HPL , 6dB gain
	    AIC3204_rset( 17, 0x06 );      // Unmute HPR , 6dB gain
	    AIC3204_rset(  9, 0x30 );      // Power up HPL,HPR
	    AIC3204_rset(  0, 0x00 );      // Select page 0
	    EVM5517_wait( 500 );           // Wait

	    /* ADC ROUTING and Power Up */
	    AIC3204_rset(  0, 0x01 );      // Select page 1
	    AIC3204_rset( 51, 0x40 );      // SetMICBIAS
	    AIC3204_rset( 52, 0xc0 );      // STEREO 1 Jack
			                           // IN1_L to LADC_P through 40 kohm
	    AIC3204_rset( 55, 0xc0 );      // IN1_R to RADC_P through 40 kohmm
	    AIC3204_rset( 54, 0x03 );      // CM_1 (common mode) to LADC_M through 40 kohm
	    AIC3204_rset( 57, 0xc0 );      // CM_1 (common mode) to RADC_M through 40 kohm
	    AIC3204_rset( 59, 0x5f );      // MIC_PGA_L unmute
	    AIC3204_rset( 60, 0x5f );      // MIC_PGA_R unmute
	    AIC3204_rset(  0, 0x00 );      // Select page 0
	    AIC3204_rset( 81, 0xc0 );      // Powerup Left and Right ADC
	    AIC3204_rset( 82, 0x00 );      // Unmute Left and Right ADC

	    AIC3204_rset( 0,  0x00 );


    Thank you in advance

    ip

  • 0 in reply to Ignasi Pascual de Labasti
    TI__Mastermind 28020 points
    Hi Ip,

    When using the PCM3070 EVM, you must use a combination of PPS to program the DSP in the part, and the control software linked in the EVM page, named PCM3070EVM-K software. This software handles the peripheral configuration of the part such as inputs, outputs, and clocks.

    Justin
  • 0 in reply to Justin Bohr
    Intellectual 850 points

    Hello Justin,

    Thank you in advance.

    On this case, using the evmc5517, with the aic3204 8 (which are almost the same as pcm3070), for this reason, there is no way I can use the pcm3070EVM-K software. We have already purchased too much evm for this project. So please, help me to find the good parameters. Documentation on that point is unclear or incomplete. I'm not asking for a complete configuration of my DSP, just I need an example of a link of the sound using the in->adc->dac->out path. It would be enought. 

    (Concerning the pps, for my solution just gives the following configuration, which still doesn't work. As you said, some parameters are missing for the good configuration of the sound codec to do what we need. But let's please forget about this point of dsp configuration, and let's focus on the in->adc->dac->out path, please)

      --- File: aic_main.asm ---
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                    225:  .sync(59) 
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                    239:   
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                     49:  .codeblock Registers target=regs, component=PCM3070App8x4x_1 
                     50:  ;----------------------------------------------------------------------------------- 
                     51:  ; Software Reset 
                     52:  ;----------------------------------------------------------------------------------- 
                     53:  	reg[  0][  1] = 0x01	; Initialize the device through software reset 
                     54:   
                     55:  ;----------------------------------------------------------------------------------- 
                     56:  ; Configure Power Supplies 
                     57:  ;----------------------------------------------------------------------------------- 
                     58:  	reg[  1][  1] = 0x08	; Disable weak AVDD to DVDD connection 
                     59:  	reg[  1][  2] = 0x00	; Enable Master Analog Power Control 
                     60:           
                     61:  	reg[  1][ 71] = 0x32	; Set the input power-up time to 3.1ms    
                     62:  	reg[  1][123] = 0x05	; Force REF charging time to 40ms 
                     63:  ;	reg[254][0] = 0x28	; Delay 40ms for REF to Power Up 
                     64:   
                     65:  ;----------------------------------------------------------------------------------- 
                     66:  ; Load miniDSP Code 
                     67:  ;----------------------------------------------------------------------------------- 
                     68:  	PROGRAM_ADC		; miniDSP_A coefficients and instructions            
                     69:  	PROGRAM_DAC		; miniDSP_D coefficients and instructions 
                     70:   
                     71:  ;----------------------------------------------------------------------------------- 
                     72:  ; Signal Processing Settings 
                     73:  ;----------------------------------------------------------------------------------- 
                     74:  	reg[  0][ 60] = 0x00	; Use miniDSP_D for signal processing 
                     75:  	reg[  0][ 61] = 0x00	; Use miniDSP_A for signal processing 
                     76:   
                     77:  	reg[  0][ 17] = 0x08	; 8x Interpolation 
                     78:  	reg[  0][ 23] = 0x04	; 4x Decimation 
                     79:   
                     80:  ; 4x Interpolation; 2x Decimation 
                     81:  ; 2x Interpolation; 1x Decimation 
                     82:  	IDAC  = 904 
                     83:  	IADC  = 904 
                     84:   
                     85:  	reg[  8][  1] = 0x04	; adaptive mode for ADC 
                     86:   
                     87:  	reg[ 44][  1] = 0x04	; adaptive mode for DAC 
                     88:   
                     89:  ;----------------------------------------------------------------------------------- 
                     90:  ; Clock and Interface Configuration 
                     91:  ;----------------------------------------------------------------------------------- 
                     92:  ; USB Audio supports 8kHz to 48kHz sample rates 
                     93:  ; An external audio interface is required for 88.2kHz to 192kHz sample rates 
                     94:  ;----------------------------------------------------------------------------------- 
                     95:  ; P=1, R=1, J=8; P=1, R=1, J=8; D=0000 (MSB); D=0000 (LSB); PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on; Delay 10ms for PLL to lock; MDAC = 8, divider powered on; DOSR = 32 (MSB); DOSR = 32 (LSB); NADC = 2, divider powered off; MADC = 8, divider powered on; AOSR = 32; NDAC = 2, divider powered on 
                     96:  ; P=1, R=1, J=8; P=1, R=1, J=8; D=0000 (MSB); D=0000 (LSB); PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on; Delay 10ms for PLL to lock; MDAC = 8, divider powered on; DOSR = 64 (MSB); DOSR = 64 (LSB); NADC = 2, divider powered off; MADC = 8, divider powered on; AOSR = 64; NDAC = 2, divider powered on 
                     97:  	reg[  0][  5] = 0x91	; P=1, R=1, J=8 
                     98:  	reg[  0][  6] = 0x08	; P=1, R=1, J=8 
                     99:  	reg[  0][  7] = 0x00	; D=0000 (MSB) 
                    100:  	reg[  0][  8] = 0x00	; D=0000 (LSB) 
                    101:  	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on 
                    102:  	reg[  0][254] = 0x0a	; Delay 10ms for PLL to lock 
                    103:  	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on 
                    104:  	reg[  0][ 13] = 0x00	; DOSR = 128 (MSB) 
                    105:  	reg[  0][ 14] = 0x80	; DOSR = 128 (LSB) 
                    106:  	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off 
                    107:  	reg[  0][ 19] = 0x88	; MADC = 8, divider powered on 
                    108:  	reg[  0][ 20] = 0x80	; AOSR = 128 
                    109:  	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on 
                    110:   
                    111:  ; P=1, R=1, J=8; P=1, R=1, J=8; D=0000 (MSB); D=0000 (LSB); PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on; Delay 10ms for PLL to lock; MDAC = 8, divider powered on; DOSR = 192 (MSB); DOSR = 192 (LSB); NADC = 2, divider powered off; MADC = 12, divider powered on; AOSR = 128; NDAC = 2, divider powered on 
                    112:  ; P=1, R=1, J=8; P=1, R=1, J=8; D=0000 (MSB); D=0000 (LSB); PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on; Delay 10ms for PLL to lock; MDAC = 8, divider powered on; DOSR = 256 (MSB); DOSR = 256 (LSB); NADC = 2, divider powered off; MADC = 16, divider powered on; AOSR = 128; NDAC = 2, divider powered on 
                    113:  ; P=1, R=1, J=24; P=1, R=1, J=24; D=0000 (MSB); D=0000 (LSB); PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on; Delay 10ms for PLL to lock; MDAC = 8, divider powered on; DOSR = 384 (MSB); DOSR = 384 (LSB); NADC = 2, divider powered off; MADC = 24, divider powered on; AOSR = 128; NDAC = 2, divider powered on 
                    114:  ; P=1, R=1, J=16; P=1, R=1, J=16; D=0000 (MSB); D=0000 (LSB); PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on; Delay 10ms for PLL to lock; MDAC = 8, divider powered on; DOSR = 512 (MSB); DOSR = 512 (LSB); NADC = 2, divider powered off; MADC = 32, divider powered on; AOSR = 128; NDAC = 2, divider powered on 
                    115:  ; P=1, R=1, J=24; P=1, R=1, J=24; D=0000 (MSB); D=0000 (LSB); PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on; Delay 10ms for PLL to lock; MDAC = 8, divider powered on; DOSR = 768 (MSB); DOSR = 768 (LSB); NADC = 2, divider powered off; MADC = 48, divider powered on; AOSR = 128; NDAC = 2, divider powered on 
                    116:   
                    117:   
                    118:  ;----------------------------------------------------------------------------------- 
                    119:  ; ADC Channel Configuration 
                    120:  ;----------------------------------------------------------------------------------- 
                    121:  	reg[  1][ 51] = 0x40	; Mic Bias enabled, Source = Avdd, 1.25V 
                    122:   
                    123:  	reg[  1][ 52] = 0x40	; Route IN1L to LEFT_P with 10K input impedance 
                    124:  	reg[  1][ 54] = 0x40	; Route CM1L to LEFT_M with 10K input impedance 
                    125:  	reg[  1][ 55] = 0x40	; Route IN1R to RIGHT_P with 10K input impedance 
                    126:  	 
                    127:  	reg[  1][ 57] = 0x40	; Route CM1R to RIGHT_M with 10K input impedance 
                    128:  	reg[  1][ 59] = 0x00	; Enable MicPGA_L Gain Control, 0dB 
                    129:  	reg[  1][ 60] = 0x00	; Enable MicPGA_R Gain Control, 0dB 
                    130:  	reg[  0][ 81] = 0xc0	; Power up LADC/RADC 
                    131:  	reg[  0][ 82] = 0x00	; Unmute LADC/RADC 
                    132:   
                    133:  ;----------------------------------------------------------------------------------- 
                    134:  ; DAC Channel Configuration 
                    135:  ;----------------------------------------------------------------------------------- 
                    136:  	reg[  1][ 20] = 0x25	; De-pop: 5 time constants, 6k resistance 
                    137:  	reg[  1][ 12] = 0x08	; Route LDAC to HPL 
                    138:  	reg[  1][ 13] = 0x08	; Route RDAC to HPR 
                    139:  	reg[  1][ 14] = 0x08	; Route LDAC to LOL 
                    140:  	reg[  1][ 15] = 0x08	; Route LDAC to LOR 
                    141:  	reg[  0][ 63] = 0xd4	; Power up LDAC/RDAC w/ soft stepping 
                    142:  	reg[  1][ 16] = 0x00	; Unmute HPL driver, 0dB Gain 
                    143:  	reg[  1][ 17] = 0x00	; Unmute HPR driver, 0dB Gain 
                    144:  	reg[  1][ 18] = 0x00	; Unmute LOL driver, 0dB Gain 
                    145:  	reg[  1][ 19] = 0x00	; Unmute LOR driver, 0dB Gain 
                    146:  	reg[  1][  9] = 0x3c	; Power up HPL/HPR and LOL/LOR drivers 
                    147:  	reg[  0][ 64] = 0x00	; Unmute LDAC/RDAC 
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                                --- File: aic_gen.asm ---
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                    495:  .codeblock Registers2 target=regs, component=Dec4xIn_1 
                    496:  reg[0][82] = 0 
                    497:   
                    498:  ; Left channel AGC initialization 
                    499:  reg[0][83] = 0 
                    500:  reg[0][86] = 32 
                    501:  reg[0][87] = 254  
                    502:  reg[0][88] = 0 
                    503:  reg[0][89] = 104 
                    504:  reg[0][90] = 168 
                    505:  reg[0][91] = 6 
                    506:  reg[0][92] = 0 
                    507:   
                    508:  ; Right channel AGC initialization 
                    509:  reg[0][84] = 0 
                    510:  reg[0][94] = 32 
                    511:  reg[0][95] = 254  
                    512:  reg[0][96] = 0 
                    513:  reg[0][97] = 104 
                    514:  reg[0][98] = 168 
                    515:  reg[0][99] = 6 
                    516:  reg[0][100] = 0 
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