Audio codec tlv320aic3268

Hi Kim,

In the script 1.0, the Fs is determined by the MCLK and the NDAC, MDAC and DOSR dividers. Configuring MDAC = 12, the Fs will be 8kHz.

#########################################################################################
# Clock configuration
# MCLK = 12.288 MHz, BCLK = 3.072 MHz, WCLK = 48 kHz (slave)
#########################################################################################
w 30 00 00 # Select Page 0
w 30 04 00 # Set DAC_CLKIN as MCLK -- default not mandatory to program
w 30 0b 81 # NDAC = 1
w 30 0c 8c # MDAC = 12
w 30 0d 00 # Program the OSR of DAC to 128 to get
w 30 0e 80 # DAC_FS = DAC_MOD_CLK / DOSR = 6.144MHz / 128 = 48kHz

#########################################################################################

For any other clock configuration, you may check the 8.3.4 Clock Generation and PLL Section in TLV320AIC3268 datasheet.

I hope this helps you. If you still have questions, please let me know.

Best regards,

Luis Fernando Rodríguez S.