• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 322 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM1807 Synchronization

KTC ...
Prodigy 150 points
Other Parts Discussed in Thread: PCM1807

Hello,

In PCM1807 datasheet, there is a section called "Syncronization with the digital audio system". Here it mentions "the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI is established."

Is there any chance that this is happening in master mode? 

Thanks

  • 0
    TI__Mastermind 27910 points
    Hi KTC,

    This should not happen in master mode since the LRCLK and BCK will be generated from SCKI. Unless the SCKI clock is interrupted the part should perform normally. This statement it targeted for when running the device in slave mode.

    Justin