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TAS5630BDKD

Jeffrey Benz
Prodigy 55 points


Dear Sir,

I am using the TAS5630BDKD package device. The device is failing in that with no load and no input I power up the PCBA and the reset line is low. the SD line is high. I bring the reset line high (3.3VDC) and the ready line goes high and the SD line goes high. This should be normal operation. What happens is if I bring the reset line low again and cycle this line low to hign the SD line will low and the ready line will stay low..I remove power and then apply power  and the SD line is immediately low and there are no  operation of the TAS563BDKD device. I am operating at 29VDC not the 50VDC I will be using. The EVM which has a different package works fine with my load and at 50 VDC. I am running PTBL mode. I see no current spike. I checked the output FETs to see if they failed and do not see anything I would assume would be a failure..  I did implement the correct resistor and capacitors to use the DKD part..  I do not see a way to attach a schematic or PCBA layout for you to review. FYI I have not installed the heat sink because the part does not get hot with no load.

  • 0
    TI__Genius 9175 points
    Hello,

    A review of your schematic would be the best place to start.
    A schematic can be attached by clicking the "Use rich formatting" on the bottom right of the text window. There will be an icon to add an image or file. Please upload schematic as a PDF.

    Are you able to get the device working the first time you power it up and SD is high, reset is high, and ready is high?
    Have you measured for shorts between outputs or output to ground?
    For PBTL, a separate inductor should be used for each output. The outputs must be tied together after the inductor rather than before.

    Best Regards,
    Matt
  • 0
    Prodigy 55 points
    Matt,
     
    I have done what you mentioned. Attached is the schematic and layout.  The zip file contain Gerber files. You should be able to open with any Gerber viewer.
     
     
    Cordially,
     
    Mr. Jeffrey A. Benz
     
    President/CEO
    IPCD Engineering Services
    8402 Nottinghill Dr.
    Indianapolis, Indiana 46234
    Ph: 513-315-1160
    Email: jbstarship@comcast.net
    Website: ipcdengineeringservices.com
     
     
     
     
     
  • 0 in reply to Matthew Beardsworth
    Prodigy 55 points
    On the first application of power it would come up with SD high, Ready high and reset high. I notice the MODE selection pins are at 1.1VDC instead of 3.3VDC after the failure. Power consumption is around 20 milliamps. I checked for shorts at the output pins. Since the SD lines does not go high when taking Reset low I assume the device is in a PPSC detection mode.
  • 0
    Prodigy 55 points
    Matt,
     
    I think I found the issue. The mode pins input leakage current is very high (100uA) I had 100 K pull-ups on the M!-M3 mode lines. Since the input lines leakage current is high the 100K pull-ups were not adequate. The TES5630B was operating in 2X BTL AD mode. This is not good for I have my output designed for 1X PBTL.  This is why the part would fail quickly without seeing any current spikes. The instantaneous turn on probably cause a huge current spike but the part failed so quickly I did not detect it. Unfortunately I have no more parts until tomorrow. I think I will be OK now. You would think control pins would be digital in nature with very low leakage current. On my schematic I had pull-ups and pull downs so that I could select the mode of operation.
     
     
    Cordially,
     
    Mr. Jeffrey A. Benz
     
    President/CEO
    IPCD Engineering Services
    8402 Nottinghill Dr.
    Indianapolis, Indiana 46234
    Ph: 513-315-1160
    Email: jbstarship@comcast.net
    Website: ipcdengineeringservices.com
     
     
     
  • 0 in reply to Jeffrey Benz
    TI__Genius 9175 points
    Hi Jeffery,

    Your assessment of the 100K pull-ups on the mode pins makes sense. On the EVM we tie the mode pins directly to VREG for this reason.
    With a part that previously faulted, have you tried running it with the mode pins connected to VREG? I would think the over current protection would protect the device from failure unless there was some current path that is not protected by the fault circuitry due to the output BTL vs PBTL mix-up.

    I also took a look at your schematic. Nothing jumped out at me but my only comment is to make sure the output transformer is sized properly for the bandwidth and power levels you expect. Core situation at low frequencies can cause current spikes that trip the Over Current protection of the amplifier.

    Here is an app note on running amplifiers with a transformer load: www.ti.com/.../sloa133.pdf

    Best Regards,
    Matt
  • 0
    Prodigy 55 points
    Matt,
     
    I saw I had to use a differential input when in PTBL mode. I now have the device working fine.
     
     
    Cordially,
     
    Mr. Jeffrey A. Benz
     
    President/CEO
    IPCD Engineering Services
    8402 Nottinghill Dr.
    Indianapolis, Indiana 46234
    Ph: 513-315-1160
    Email: jbstarship@comcast.net
    Website: ipcdengineeringservices.com