TAS5754M/56M Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)

Sadanori Kato

Other Parts Discussed in Thread: TAS5754M

Hi,

Could you please tell us how to set all appropriate registers for the clock distribution and etc if using 3-wire PCM at the 192kHz processing by using the hybridflow5 ?

The condition which we would like to use is shown as below.

MCLK: Kept the Low Level

SCLK: 12.288MHz

LRCK: 192kHz

SDIN: Stereo 24bit I2S Data

Best regards,

Kato

over 9 years ago

0 Damian Lewis over 9 years ago

TI__Mastermind 34775 points

Hi Kato-san,

The device can auto setup the clocks for 3-wire mode. You have to tell the device to ignore MCLK error, since there's no MCLK and set the PLL source clock to SCLK, default is MCLK.

0 Sadanori Kato over 9 years ago in reply to Damian Lewis

Guru 36540 points

Hi Damian-san,

Thank you for your prompt reply.

I have tried the evaluation by using the TAS5754M evm and confirmed that it works in the 3-wire pcm mode.

The settings of this operation mode are shown as below.

I greatly appreciate your cooperation.

Best regards,

Kato

0 Damian Lewis over 9 years ago in reply to Sadanori Kato

TI__Mastermind 34775 points

Hi Kato-san,

That's correct...great job!

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TAS5754M/56M Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)