TLV320AIC3104 phase shift after reset

Hi, Markus,

Welcome to E2E and thank you for your interest in our products.

Could you provide a schematic and the clocks frequencies that you're using? It is to have a better approach of this issue. Additionally, have you tried to enable the MCLK, WCLK and BCLK after write in the registers? Finally, do you know if this issue appears when you use less codecs?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

I can't upload a schematic, but I can list the connections to the codec ...

Pin: Label – Connection
1: MCLK – to MCLK clock buffer out through 22 ohm resistor, clock buffer in is XTAL 24.576MHz, clock buffer out also goes to OMAP-L138
2: BCLK – to BCLK clock buffer out through 22 ohm resistor, clock buffer in is ACLKX from OMAP-L138
3: WCLK – to WCLK clock buffer out through 22 ohm resistor, clock buffer in is AFSX from OMAP-L138
4: DIN – to OMAP-L138 through 22 ohm resistor
5: DOUT – to OMAP-L138 through 22 ohm resistor
6: DVSS – digital ground
7: IOVDD – 3.3V supply
8: CSL – to I2C switch SC (TCA9548A)
9: SDA – to I2C switch SD (TCA9548A)
10: LINE1LP – positive output from diff preamp (left)
11: LINE1LM – negative output from diff preamp (left)
12: LINE1RP – positive output from diff preamp (right)
13: LINE1RM – negative output from diff preamp (right)
14: LINE2L – to 3.3V supply through 10k ohm resistor
15: MICBIAS – no connection
16: LINE2R – to 3.3V supply through 10k ohm resistor
17: AVSS1 – digital ground
18: DRVDD – 3.3V supply (analog)
19: HPLOUT – no connection
20: HPLCOM – no connection
21: DRVSS – digital ground
22: HPRCOM – no connection
23: HPROUT – no connection
24: DRVDD – 3.3V supply
25: AVDD – 3.3V supply (analog)
26: AVSS2 – digital ground
27: LEFT_LOP – to line driver (left)
28: LEFT_LOM – to line driver (left)
29: RIGHT_LOP – to line driver (right)
30: RIGHT_LOM – to line driver (right)
31: RESET – to OMAP-L138
32: DVDD – 1.8V supply

3.3 V supplies and 1.8V supplies bypassed with 0.1uF and 1.0uF

Clock buffers are three CDCVF2310.

Register 8 (BCLK/WCLK configuration) has always been written to early in the sequence. The sequences have been either registers 1,3,7,8,9,... in order or 1,3,101,8,9,7,... in order. Do you suggest writing to register 8 as the last item (after turning on the ADC/DAC with registers 15,16)?

We have tried register 101 at the beginning or at the end, with no effect.

Will the codec still function -- go through soft reset and register writes -- if MCLK is turned off? The clock buffers have a enable/disable switch, but it is hardwired enabled in our PCB. Do you think it is worthwhile to making the changes to initialize the codec with MCLK turned off?

I don't know what happens if I only configure 2 codecs and ignore the rest. I can try that and test phase difference between them.

Thanks,
Markus

Hi Luis,

I did some additional tests at the software level and looked at the behavior with just 2 codecs.

I only configured the ADCs and left the DACs off/unconfigured. I did a soft reset & register write on just one codec at a time while measuring phase shift between two codecs (inputs connected to the same 9.6kHz input signal from a function generator).

Single (48kHz) vs. Double (96kHz) ADC Rate

48kHz -- register 3 = default, register 7 = default

• phase shift takes on two values that are multiples of about 1/25MHz, shifts after soft reset

96kHz -- register 3 = 0x20, register 7 = 0x60

• phase shift takes on four values that are multiples of about 1/25MHz, shifts after soft reset

Use PLL vs CLKDIV, register 101

PLL -- register 101 = default

• no difference observed

CLKDIV -- register 101 = 0x01

• no difference observed

Power on the ADC before clock setup

ADC ON (registers 19 and 22 = 0x87) before writing to register 101

• no difference observed

ADC ON (registers 19 and 22 = 0x87) after writing to register 101

• no difference observed

Typical sequence over I2C for one codec:

1. reg 0 = 0x00
2. reg 1 = 0x80
3. reg 9 = 0xF6
4. reg 21 = 0xF8
5. reg 24 = 0xF8
6. reg 3 = 0x20 (omitted for single rate)
7. reg 7 = 0x60 (omitted for single rate)
8. reg 101 = 0x01 (omitted for PLL)
9. reg 19 = 0x87
10. reg 22 = 0x87
11. reg 15 = 0x00
12. reg 16 = 0x00

Next I will look at starting up the codec with MCLK, BCLK and WCLK turned off, then turning them on after the ADC is on. This will require a non-trivial hardware change for us.

Thanks,

Markus

Hi, Markus,

Have you observed differences with your last test? Did it get solved?

Best regards,
Luis Fernando Rodríguez S.

Problem is not solved. Only observation is that the phase shift is a little different when running the ADC in single rate (48 kHz) rather than double rate (96 kHz).

Just modified our PCB yesterday so that the enable/disable pins on the clock buffer serving MCLK to codecs are wired to a GPIO from the CPU. Will post again once tests are completed while doing a soft reset / register writes with the MCLK disabled.

I'm happy to say that this problem has been solved.

The glitch-free enable pins (1G/2G) on all the clock buffers -- for MCLK, BCLK, WCLK going to all  the codecs -- was rewired to a GPIO port. That way we could disable the clocks to the codecs while doing a soft reset and write to registers. Previously, we had 1G/2G wired to +3.3V so the clock buffer outputs were always on.

The I2C switch between CPU and codecs was set to broadcast the I2C register writes simultaneously to all the codecs during initialization. I suppose you could write to each one in series as long as the clocks stay disabled until after you turn on the ADCs (but we did not test that).

Here is our start-up sequence:

1. initialize PLL, GPIO, I2C
2. suppress all  the clock buffer outputs
3. initialize UART
4. hardware reset of I2Cmux and all the codecs
5. software reset of all codecs simultaneously, and set up the registers
6. enable the clock buffer outputs (MCLK/BCLK/WCLK)
7. initialize McASP
8. start background processes

Here is what works to eliminate the phase shift (can be run at any time):

• Resetting an individual codec without simultaneous resetting all the others
• Disable MCLK but then enable MCLK the step before turn on ADC
• Not doing soft-reset steps above after a hardware reset

• Disable MCLK/BCLK/WCLK during hardware reset
• Configuring the DACs or turning DACs ON/OFF.
• During start-up, you can initialize McASP (for BCLK/WCLK) after the codecs are set up. Its OK for the codecs to be getting MCLK without BCLK/WCLK for a while, as long as MCLK was not going out to the codecs during a soft-reset & configuration as described above. 
• The order of codec register writes doesn't  matter except for registers 19 and 22 to turn ON the ADC
• Using the PLL or CLKDIV in the codec