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TLV320AIC3110 queries

Srijan Ashok
Intellectual 1045 points
Other Parts Discussed in Thread: TLV320AIC3110

Hello Folks,

1. By providing proper signals( I2S,MCLK,BCLK,WCLK), Is Codec able  to generate audio on Headphone(connected) with default setup?
        if not, what would be the initialization sequence to achieve that?
    2. It would be best if you can provide sample code for initializing the codec(AIC3110).
    3. I tried to generate the beep sound but i find no response from the codec.and also i am not getting the expected clocks from the PLL.kindly suggest where could  be the issue?
Register settings and input clocks are provided below
    
Input clocks
            MCLK : 12.28Mhz(approx)
            WCLK : 48Khz(approx)
            SCLK  : 3Mhz(approx)
Register Settings

Register

Value

Comment

0x04

0x03

Codec clock takes PLL clock

0x05

0x91

P : 1, R : 1

0x06

0x06

 

j : 6.929

0x07

0x03

0x08

0xA1

0x0B

0x85

NDAC : 5

0x0C

0x83

MDAC : 3

0x0D

0x00

DOSR : 128

0x0E

0x80

Clock monitoring Registers

0x19

0x04

CLK Div : DAC CLK (Dac fs)

0x1A

0x81

Clk out divider : 1

0x33

0x10

CLk out pin : GPIO Pin


with the above settings i monitor clocks via GPIO pin,below are the values i got but it is not as expected

CLocks

Monitored

Expected

PLL Clk

74Mhz

84.67Mhz

DAC Clk(Dac fs)

14Mhz

44.1Khz

DAC Mod Clk

5.1Mhz

5.64Mhz

Thanks,
Srijan

  • 0
    TI__Guru* 84915 points

    Hi, Srijan,

    The codec is not able to generate audio on headphone output with the default setup. Please take a look of the 5.5.12 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs. It show how to setup the TLV320AIC3110 in playback mode with fs=44.1kHz and MCLK=11.2896MHz.

    Regarding the beep generator, the following document mentions how to configure it properly: http://www.ti.com/lit/an/slaa446/slaa446.pdf.

    Your register configuration seems to be in order, you should obtain the expected results. Could you provide your script to review it?

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 50 points
    Hi Luis and Srijan,

    Thanks in advance.

    Now i am able to generate the beep tone successfully, by setting the DAC PRB as PRB_P25.

    But the Codec initialization doesn't seems good with the given settings in Datasheet(Section : 5.5.12).
    Codec (AIC3110) is interfaced with the bridge IC (CM108B - USB to I2S converter) which takes the audio signal from the USB and convert into I2S format for codec.

    The MCLK,WCLK,SCLK is provided by the same bridge IC.

    Monitored Input clocks are
    MCLK : 12.28Mhz(approx)
    WCLK : 48Khz(approx)
    SCLK : 3Mhz(approx)

    With the above setup and codec initialization , I hear a noise sound on the headphone when ever i tried to play any audio.

    Following are my intialization script.

    w 24 0x00 0x00//Page 0
    w 24 0x01 0x01//Reset
    delaycntr =90000;
    while(delaycntr--);
    w 24 0x04 0x03//PLL : MCLK CODEC : PLL Generatd
    w 24 0x05 0x91//R = 1 P = 1
    w 24 0x06 0x06 // J = 6.929
    w 24 0x07 0x03
    w 24 0x08 0xA1

    w 24 0x1B 0x00//I2S 16 Bit
    w 24 0x0B 0x83
    w 24 0x0C 0x85
    w 24 0x0D 0x00
    w 24 0x0E 0x80

    w 24 0x74 0x00
    w 24 0x44 0x00 //DRC Threshold -3db
    w 24 0x41 0xD4 //Left Volume = -21.5db
    w 24 0x42 0xD4 //Right Volume = -21.5db

    w 24 0x00 0x01
    w 24 0x21 0x4E
    w 24 0x1F 0xC2// HP o/p driver enable
    w 24 0x23 0x44
    w 24 0x28 0x06
    w 24 0x29 0x06
    w 24 0x2A 0x1C
    w 24 0x2B 0x1C

    w 24 0x20 0xC6
    w 24 0x24 0x92
    w 24 0x25 0x92
    w 24 0x26 0x92
    w 24 0x27 0x92

    w 24 0x00 0x00
    w 24 0x3C 0x0B
    w 24 0x00 0x08
    w 24 0x01 0x04
    w 24 0x00 0x00
    w 24 0x3F 0xD6
    w 24 0x40 0x00


    //Test with GPIO pin
    w 24 0x19 0x03
    w 24 0x1A 0x81
    w 24 0x33 0x10
  • 0 in reply to SatheeshRamasamy
    TI__Guru* 84915 points
    Hi, Satheesh,

    It seems that the problem could be related with registers P0/R7 (PLL D-VAL MSB) and P0/R8 (PLL D-VAL LSB). These registers are configured as 0x03A1, which actually would be D=0929. So, the real value of J.D is 6.0929. In order to obtain D=9290, the registers must be configured as 0x244A (P0/R7 = 24; P0/R8 = 4A). Could you try with these values, please?

    Additionally, I noticed that you're expecting DAC Clk = DAC_fs = 44.1kHz. Actually, DAC_Clk value would be calculated as DAC_Clk = CODEC_CLKIN/NDAC.

    I hope this helps you. Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 50 points

    Hi Luis,

    Sorry for my late reply,since we hanged up with other issues.

    So now i am able to make the corrections and test.but still i found the same noise over head phone.below given my configurations for your reference.

    I/p MCLK : 12.28Mhz, DAC fs required : 48Khz

    With the above script config(R =1,P =1,NDAC = 3,MDAC =5),i modified P0/R6 : 0x07, R7 : 0x13, R8 :0x88 (i.e J = 7.5000).

    and also i monitored DAC_MOD_CLK : 6.144Mhz(which seems to be correct,because my DOSR is 128d).

    As per this, the clocks are tuned correctly,but still the noise presents.kindly help me in this.

     

     

    Thanks in advance,

    Satheesh Ramasamy

  • 0 in reply to SatheeshRamasamy
    Prodigy 50 points
    Hi Luis and Srijan,

    The issue has been resolved, its problem with the bridge IC which not able to generate a propper MCLK (varying in between).

    Now everything ok,with the above configurations i am able to hear a propper audio.

    Thanks guys for your valuable support


    Regards
    Satheesh Ramsamy