• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 29 subscribers
  • Views 419 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM49352 - Clocking configuration

Shawn Nageli
Prodigy 180 points

I have been through the datasheet, posts and been over the slaa469.pdf.  I just want to verify the clocking in our setup.

We will be using the AUX input (Stereo) with the HPL/HPR_OUT (Stereo) output.  We are planning to perform some DSP on the this signal so will be routing in and out of the ADC and DAC.

In our implementation we will have the LM49352 also serve as the I2S master as well on Port1 CLK and SYNC.

We are planning to run a 12.288MHz Oscillator into MCLK.  I understand this will need to be frequency-locked with the Port 1 CLK and SYNC.  We have another part that is dependent on a frame clock of either 64*Fs or 128*Fs. With that said I would assume we would set register 0x52h SYNC_RATE to 64 and that should then set our CLK (Bit Clock) to 64*Fs, correct?  In short we need the following:

  • MCLK - 12.288MHz
  • PORT1_CLK (Bit Clock) - 3.072MHz (64*Fs)
  • PORT1_SYNC (Frame Clock) - 48kHz

Also, with using a native audio clock on MCLK we would then set the ADC clock (0x20h) and DAC clock (0x30h) to use MCLK rather than the PLL, correct?

Thanks,

Shawn

  • 0
    TI__Guru** 109545 points
    Hi Shawn,

    Audio Port 1 can be set to master through register 0x50 bits 4:3. You can control the clock generator for Audio Port at register 0x51, the clock source must be selected from DAC or ADC (bit 6) and can be adjusted with the half-cycle divider (bits 5:0).
    Then the Sync_Rate can be adjusted through register 0x53 (bits 2:0).
    Yes, PLL can be bypassed to source ADC and DAC with MCLK directly.
    You can see figure 57 in order to find the best route for your clock signals.

    So we could have the following:
    - MCLK = 12.288MHz
    - Set MCLK as clock source for ADC/DAC
    - Set Audio Port as master (register 0x50 bit 4:3 = 11)
    - Select either ADC/DAC as clock source for Audio Port Clock Generator (register 0x51 bit 6)
    - Set the Half_Cycle_CLK_Divider, as the description says "Program this divider with the required division multiplied by 2, and subtract 1." so as we need BCLK = 3.072MHz which is BLCK = MCLK/4, according to the divider description DIVIDER = (4*2)-1 = 7 so register 0x51 bit 5:0 = 001101
    - Set Sync_Rate to 64 in order to get Sync = 48kHz (register 0x53 bit 2:0 = 111), since Sync = BCLK/64

    This may be a little confusing because usually the frame clock is set first by dividing the master clock, and then the bit clock adjusts as X times the frame clock. In this case we first set bit clock dividing the master clock and then adjust the frame clock (sync) by dividing the bit clock.

    Best regards,
    -Ivan Salazar
    Texas Instruments
  • 0 in reply to Ivan Salazar
    Prodigy 180 points
    I appreciate the feedback. Yes it is confusing as you have already mentioned that normally the frame clock is set first with the division of the master clock. The settings make sense. Will give this a go.