Sample synchronization of multiple AIC33 CODECs

Hi, David,

In all the multi-channel systems with codecs, there's a negligible delay between each channel data. This is because all the multi-channel data is sent on the same line. So, the data from each channel must be sent one after other. However, this is not an audible delay and it can be considered negligible.

Please take a look of the following document: http://www.ti.com/lit/an/slaa508/slaa508.pdf. It is an example of how to synchronizing multiple parallel TLV320ADC3101. It could be useful for your application.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis

We are not too concerned about the transmission delay of the data as we are storing and then processing the data. We are interested in the precision of the sampling of the data across all channels in a multi codec configuration. 

In the first document it states: "Verification of this method and programming was performed using an Audio Precision test instrument by measuring the phase difference between each channel."

Does this mean the phase based on the sample clock or based on the internal oversample clock (256*Fs)?

Are all of the channels sampled at exactly the same time?

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Hi Luis

Thank you for the response, however the answer is still not clear. You seem to be implying that the channels are phase shifted based on their position in the TDM stream. i.e the data clocked out are not simultaneously sampled. Even for a single codec.

1. In the case of a single codec clocking out left and right channels are the channels sampled simultaneously? Again, we know the data is shifted out serially on the digital interface and we're not concerned about the delay in receiving the digital data, we are interested to know if there is a phase difference between the sampled data. 

2. In this document slaa508.pdf, it states 

"Using a multichip solution sometimes requires synchronization of channels such that all of the devices operating in parallel operate in lock-step with each other to prevent phase shift errors between channels."

This is what we need to be clear on. If we had 4 codecs (8 channels) of data can we be sure all 8 channels were sampled on exactly the same oversample clock edge (simultaneous sampling). Again we know there is a delay in the digital data being serially transmitted and we're not concerned about the time delay between receiving the data.

Thanks

Dhar

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Hi Luis - if you don't have the answer to our question, could you please move it up the food chain over at TI.

Again, are the 2 channels in the AIC33 simultaneously sampled, or is there a phase delay based on some function of the serial output stream you mentioned above?

Thanks

Bump

Hi Luis,

The serial digital interface that streams frames from point A to point B should have no bearing on sampling delay, or whether the two channels are simultaneously sampled. Your comments suggest that there might be a "negligible" "non-audible" delay. We take this to mean a "finite non-zero delay that we won't hear", which suggests "not simultaneous sampling".

Simultaneous sampling implies that both data points in the output frame represent the exactly identical point in time in terms of the oversampling clock edge and the pipeline delay in the converter. This is not necessarily implied or guaranteed even if both channels are derived from the same oversampling clock (ie. misaligned pipeline between the two channels or between two or more CODECS).

As our application is audio beamforming, this characteristic is vitally important (we are dealing with fractional sampling delays). It is equally as important when we extend the case to multiple CODECs.

Could you please forward our question up as I suggested...

Thanks

Thanks, Luis!

Hi, David,

Please see the answer from my colleague:

If MCLK is provided to all the chips at the same time the parts should be synchronized in oversampled domain.

Conditions:

1. PLL must not be used.
2. Configure all registers first without MCLK.
3. Once  the converters are powered, provide MCLK.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis

In your first response you linked this document

slaa508.pdf

This states that the MCLK is supplied to 1 master codec which produces BCLK that is then used as the source for all the other slave codecs.

This is not the same as the host supplies the MCLK that is used by all codecs as the source.

Please let us know which of these configurations is the correct one and the reason the other one is incorrect.

Thanks

Dhar

Hi, Dhar,

Several configurations are possible in these cases.

Actually, it would depend of the kind of configuration that you're looking for. The MCLK can be provided to all the codecs even if they are configured as master or slave. Normally, it is used to generate the sampling frequency or to generate the BCLK/WCLK (in master mode case).

So, in order to synchronize multiple codecs, the devices can be used as described in the slaa508.pdf. However, there's the possibility to use the master clock for all the devices  just to generate the sampling frequency. I mean, in the slaa508.pdf the MCLK is used to generate the BCLK and WCLK but it will be used only in one codec to generate the sampling frequency. The rest of the codecs will use the BCLK (for example) to generate the sampling frequency.  In case where the MCLK is provided to all the codecs, it can be used to generate the BCLK and WCLK in one codec and generate the sampling frequency in all the codecs.

So, the only difference is which clock is used to generate the sampling frequency.

Best regards,
Luis Fernando Rodríguez S.