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Regarding NDAC and NADC

1258021
Genius 5120 points

Other Parts Discussed in Thread: TLV320AIC3204

Hi,

I am trying to understand the PLL Example Configurations which are in the TLV320AIC36 Codec Data Sheet. (Table 5-21).

Let's assume that AOSR = DOSR = 128, I have selected for a sampling frequency of 44.1KHz.

ADC_MOD_CLK = DAC_MOD_CLK = 128 * 44.1KHz

Now for selecting MDAC and MADC I am using following equations (MADC * AOSR) / 32 >= RC PRB_Rx. I want to use processing block PRB_R1. For this processing block RC = 6. i.e. MADC >= 1.5. Similarly when I use the equation (MDAC * DOSR) / 32 >= RC PRB_Py. I have chosen PRB_P1. i.e. MDAC >= 2.

As given in table lets assume MADC = MDAC = 3.

Now using CODEC_LCKIN = NADC * ADC_CLK = NDAC * DAC_CLK. As ADC_CLK and DAC_CLK are same NADC = NDAC. But what value do I have to chose here. I don't understand how they have chosen NDAC = NADC = 5.

I am using MCLK with a frequency value of 12MHz.

For calculating the values I was using Design and Configuration Guide for the TLV320AIC3204 and TLV320IAC3254 which is available at the following URL: http://focus.ti.com/lit/an/slaa404c/slaa404c.pdf. I am referring Section 2.2 in that PDF.

The following are my doubts

Can I select MADC = 2 and MDAC = 3 ?

While calculating NADC and NDAC, as long as the constraints which are given under  step-3 are met, can we use NADC and NDAC any value from 1 to 128. Step - 3 is available in Section 2.2 Table - 1.xx

 

Thanks in Advance

  • 0
    TI__Mastermind 46195 points

    Hi,

    Let's go through this step-by-step:

    1. 12MHz MCLK is used and a sample rate of 44.1kHz is desired.
    2. As you mentioned, you would like to use an OSR of 128. This results in an oversampling rate of 5644.8MHz for both ADC and DAC modulator clocks.
    3. Setting MDAC and MADC as 2 yields M*OSR = 256, which is larger than or equal than the PRB RC*32. We can also choose MDAC and MADC as 3 as shown in the datasheet. This will yield an ADC and DAC CLK of 16934.4 kHz.
    4. CODEC_CLKIN is common for both ADC and DAC paths. So, by definition, they must be equal. Since ADC_CLK and DAC_CLK are also equal, then that means that NADC and NDAC will also be equal. Select an NADC and NDAC value that falls within the supported range for the PLL. For NADC and NDAC  equal to 5, this yields 84.672 MHz.
    5. As a last step, divide 84.672 MHz by 12 MHz and that will give 7.0560. J can be 7, and D can be 0560.

    Regarding your last question. You can select MADC different than MDAC. The only issue is finding an NADC and NDAC value that will satisfy CODEC_CLKIN. For some cases, for example, 8kHz sampling, the DOSR can be set to 768 and AOSR to 128. In this case, DOSR would be set 6 times smaller than AOSR. Other cases, where, say DOSR = 64 and AOSR = 128 is desired, then MDAC will be set 2 times larger. In general, you could also decrease N to increase M and vice-versa. However, in cases where it is desired to run the miniDSPs in lock-step (e.g. pass data from miniDSP_A to miniDSP_D), then ADC_CLK and DAC_CLK should also remain equal. In fact, the ADC_CLK and DAC_CLK are used to derive the clocks required for processing (either through PRB or miniDSP).

    We were testing PLL calculator functionality to create a list of values using iteration methods (which can also provide approximations). You can enable this beta app by going to "[Installation Folder]\DATA\EVM\AIC3254\AIC3254.ini" of the AIC3254 CS and adding the last line below to that file. Replace "AIC3254" text with "AIC36" when using with AIC36.

    (6)(0) = "Tools"
    (6)(1) = "EEPROM Writer", "EVM\AIC3254\EEPROM_WRITER\EEPROM_WRITER.vi"
    (6)(2) = "PLL Calculator", "EVM\AIC3254\PLL_CALC\PLL_CALC.vi"

    Thank you for your interest in TI products.

    Regards,

    J-