Setting TLV320AIC3268 as I2S2 master (generate own clock for I2S2)

Yuval Izhaki

Dear Sir \ Madam

I have designed an audio product best on the AIC3268 codec with SPI interface (for configuration)

I have double check the hardware design to find no fault (all power signal tested and I am providing MCLK signal of 12.288 Mhz to pin 18 (MCLK) and programming the AIC3268 via SPI (works for read and write)

also check reset signal is in High condition and get into conclusion that there is no hardware problems or design issue.

I find it difficult to set the codec in master mode : routing ADC data to serial interface 2 while interface act as master and generate all I2S clocking signals

the ADC is feed from 2 microphones powered from MIC_BAIS_EXT and connected to IN1 and IN2

currently I see no signal (I2S) signals on the output and no bais voltage for the microphones after programming

Please help me set the AIC3268 in work condition

Best regards

Yuval Izhaki

over 9 years ago

0 Luis Fernando Rodriguez S. over 9 years ago

TI__Guru* 84915 points

Hi, Yuval,

The master mode often is not clear to be configured in the AIC3268. Could you provide your register configuration, please? It is just to have a better approach of this issue.

Thank you.

Best regards,
Luis Fernando Rodríguez S.

0 Yuval Izhaki over 9 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 200 points

Dear Luis

Thank you for the fast replay

Please see below the register setup as programmed into the AIC3268 :

(the register setup was based on script 7.2 in "slac654 script example for AIC3268)"

reg_value REG_Section_program[] = {
/*#########################################################################################
# Codec Software Reset
#########################################################################################*/

    { 0x00,0x0 },                     // Initialize to Page 0
    { 0x7F,0x00},                 // Initialize to Book 0
    { 0x01,0x01},                 // Initialize the device through software reset
    //1 msec delay required here
/*#########################################################################################
# FIFO Configuration
#########################################################################################*/
    { 0x00,0x00},                 // Select Page 0
    { 0x7f,0x78},                 // Select Book 120
    { 0x32,0x80},                 // Enable DAC FIFO
    { 0x7f,0x64},                 // Select Book 100
    { 0x32,0x80},                 // Enable ADC FIFO
    { 0x7f,0x00},                 // Select Book 0
/*#########################################################################################
# Power and Analog Configuration
#########################################################################################*/
    { 0x00,0x04},                 // Select Page 4
    { 0x77,0xC0},                 // Disable miniDSP power-up sync with ASI
    { 0x00,0x00},                 // Select Page 0
    { 0x0d,0x80},                 // 80 Program DOSR = 128 *************
    { 0x14,0x80},                 // Program AOSR = 128
    { 0x00,0x01},                 // Select Page 1
    { 0x01,0x00},                 // Disable weak AVDD to DVDD connection, make analog supplies available
/*#########################################################################################
# For BiQuad Configuration see Script '0.1.txt'
#########################################################################################*/
/*#########################################################################################
# Clock configuration
# MCLK = 12.288 MHz, BCLK = 3.072 MHz, WCLK = 48 kHz (slave)
#########################################################################################*/
    { 0x00,0x00},                 // Select Page 0
    { 0x04,0x00},                 // Set ADC_CLKIN as MCLK -- default not mandatory to program
    { 0x12,0x81},                 // Power Up NADC, NADC = 1
    { 0x13,0x82},                 // Power Up MADC, MADC = 2
    { 0x14,0x80},                 // Program the OSR of ADC to 128,ADC_FS = ADC_MOD_CLK / AOSR = 6.144MHz / 128 = 48kHz
/*#########################################################################################
# Audio Serial Interface Routing Configuration - Audio Serial Interface #2
# ASI #2 connected to BCLK2, WCLK2, DIN2, and DOUT2 pins
#########################################################################################*/
    { 0x00,0x04},                 // Select Page 4
    { 0x11,0x00},                 // Audio Serial Interface #2 = I2S mode, 16-bit
    { 0x1a,0x25},                 // For Audio Serial Interface #1,Select BCLK2 as BCLK out and WCLK2 as WCLK out
    { 0x17,0x01},                 // Route ADC data to Audio Serial Interface #2
    { 0x18,0x50},                 // ASI#2 Left Channel data sent to Left Channel DAC,ASI#2 Right channel data sent to Right Channel DAC
    { 0x45,0x04},                 // Select WCLK2 pin as WCLK for Audio Serial Interface #2
    { 0x46,0x04},                 // Select BCLK2 pin as BCLK for Audio Serial Interface #2
    { 0x47,0x22},                 // Select DOUT2 pin as DOUT for Audio Serial Interface #2
    { 0x48,0x20},                 // Select DIN2 pin as DIN for Audio Serial Interface #2
    { 0x76,0x16},                 // Only ASI#2 Routed to DAC miniDSP Data Input 1
/*#########################################################################################
# Signal Processing Settings
#########################################################################################*/
    { 0x00,0x00},                 // Select Page 0
    { 0x3d,0x01},                 // Set the ADC PRB Mode to PRB_R1
/*#########################################################################################
# ADC Input Channel Configuration --- IN2L / IN2R
#########################################################################################*/
    { 0x00,0x01},                 // Select Page 1
    { 0x08,0x00},                 // Set the input common mode to 0.9V
    { 0x34,0x20},                 // Route IN2L and CM1 to LEFT ADCPGA with 20K input impedance
    { 0x36,0x80},
    { 0x37,0x20},                 // Route IN2R and CM1 to RIGHT ADCPGA with 20K input impedance
    { 0x39,0x80},
    { 0x3b,0x0c},                 // Left Channel Analog ADC PGA = 6 dB -> Overall Channel Gain of 0dB
    { 0x3c,0x0c},                 // Right Channel Analog ADC PGA = 6 dB -> Overall Channel Gain of 0dB
    { 0x3d,0x00},                 // ADC Analog programmed for PTM_R4
    { 0x00,0x00},                 // Select Page 0
    { 0x51,0xc0},                 // Power-up ADC Channel
    { 0x52,0x00},                 // Unmute ADC channel and Fine Gain = 0dB
};

0 Luis Fernando Rodriguez S. over 9 years ago in reply to Yuval Izhaki

TI__Guru* 84915 points

Hi, Yuval,

It seems to be related with the Audio Serial Interface #2 configuration.

First, it is necessary to enable all the clock dividers. So, NDAC (Book 0 / Page 0 / Register 11) and MDAC (Page 0 / Register 12) must be enabled too.

Then, BCLK and WCLK outputs must be enabled. The secondary BCLK N divider must be powered up (Book 0 / Page 4 / Register 28). The BCLK divider can be configured with the same register. The secondary WCLK N divider must be powered up too (Book 0 / Page 4 / Register 29). Its value depends of the DAC_Fs.

Please take a look of this registers and let me know if you have more questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Audio

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Setting TLV320AIC3268 as I2S2 master (generate own clock for I2S2)