Other Parts Discussed in Thread: PCM1794A
Hi I am very interested in your DAC PCM1794A, which supports 16 bit and 24 bit operation. I am looking at using the 24 bit stereo operation @ 192kHz.
When selecting my system clock, Fsys, it would likely be a multiple of 48 (24 bits * 2 channels * 192000).
Your chip supports 192 * Fs as a system clock speed which is great. However, many digital audio transceivers do not support a system clock of 192Fs, and only 128Fs, 256Fs, 512Fs. In order to choose a system clock that is going to be favorable for the entire topology of the circuit, I was looking at configuring an I2S interface with 64 bit word, 32 bits per channel to communicate with the DAC. Will the chip truncate any bits sent to it beyond the first 24 that are sent to it on each channel? Would there be any issues sending 24 bits + 8 null bits per channel so that I can use a system clock of Fsys of 256*fs?
Thanks,
Kevin
