TAS2505 codec problem with PLL from BCLK

Hi Ivan,

these are our register settings:

The frequency of BCLK and MCLK is 2048kHz.
We tried PLL*4, *8 and *16. There is no difference beteween these settings.

Best regards
Florian

We also tried different data lengths (32 / 16 bit).
It works a few times, but then something happens in the chip and we have to send a reset command and set all registers again.
After these steps the cips works again until the problem occurs again.

With an external clock for the codec this problem will not occur.

It would be great if this fact would be mentioned in the datasheet!

Stopping the clocks randomly will cause undefined behavior. The TAS2555 must be powered down before the clocks stop and powered up after the clocks start. It is not necessary to re-program all registers from scratch but the DAC, PLL and dividers must be turned off and back on to avoid problems.

Please see section 2.6 in the application reference guide. It explains the reasoning behind having a controlled power up and down sequence and that stopping clocks randomly is not allowed. 

power down sequence (before stopping clocks):

1. mute digital volume control
2. power down DAC channel
3. power down output drivers
4. wait for power status flag in P0R37
5. power down MDAC divider
6. power down NDAC divider
7. power down PLL

power up sequence (after starting clocks):
1. power up PLL
2. wait 10ms for PLL to stabilize
3. power up NDAC divider
4. power up MDAC divider
5. power up output drivers
6. power up DAC channel
7. unmute digital volume control