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TLV320AIC23B problem with I2S

Holger50360
Prodigy 80 points

Hello,

I tried to interface with the AIC23 in DSP mode, USB mode, slave mode, 96 kHz samples, supplying both MCLK and BCLK with the same 12 MHz clock.

Is this possible? It does not seem to be: DOUT is unsynchronized to LRCOUT and its shortest bits look like 6 MHz BCLK.

SPI commands are working fine, my configuration is:

registers in hex:     F=1FF, 0=117, 1=117, 2=1F7, 3=1F7, 4=12, 5=08, 6=22, 7=13, 8=1D, 9=01

best regards

Holger

  • 0
    TI__Mastermind 28585 points

    In slave mode, the BCLK will determine how fast the data bits are clocked out. 

     

    The actual sample rate is set by MCLK and the register settings. This means that your LRCK must be an exact multiple of MCLK and at exactly the sample rate.

     

     

  • 0
    Prodigy 80 points

    I found the solution. Problem is the reset register F which I wrote first to 1FF.
    Everything works fine as long as I don't touch it. When I write 1FF the codec ignores BCLK, LRCIN/OUT and sends data with 6 MHz.

    So, don't touch the reset register.

    bye
    Holger