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TAS5760M for I2S format

Other Parts Discussed in Thread: TAS5760M, TAS5731M

Hello

The data sheet of the TAS5760 does not have I2S information in detail.

I would like to have the inforamtion of I2S regarding to timing and format etc.

Thanks

  • Hi, Jin,

    The information about I2S in the TAS5760M datasheet can be found on page 23. If you need detailed information about I2S, you can take a look to the datasheets of the TAS57xx devices (like TAS5731M), this family of amplifiers have I2S audio input. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Hi Diego
    Thank you for answer.
    I would like to ask you as below.
    ================= below ==================
    I checked that The Data sheet TAS5760M On Page 23 has Idle current Vs PVDD. Sample Rate of TAS5730M is up 48KHz but it of TAS5760M is up to 88KHz.
    Because the designer for Audio is beginner, please give me recommended I2S information in detail.
    =========================================
    Thanks
  • Hi, Jin,

    My apologies, the page number I mentioned is a typo, the information of I2S in this datasheet is located on page 28. About your questions of I2S spec, you are right, the parameters of the TAS5731M are related to the maximum spec for the device (48KHz), but the relation of these parameters can be applied relatively to the TAS5760M. Can you please provide more information about the detailed specs you need?

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Hi Diego
    Thank you for Answer.
    I would like to have questions as below regarding to TAS5760M.
    ========================= Below ==============================
    1. Selection Capacitor for PVDD in terms of output Audio power.
    - In case of operating limied to 20W Audio power total, How much Capacitor Value for PVDD?
    - Application not of TAS5760 recommend that 470uF for PVDD.
    - Designer want to select cost-effective value of Capacitor

    2. Selection MCLK
    - Regarding to the data heet of TAS5760M Page on Table 3, is it right Caculation MCLK regaring to fs = 44.1KHz as the below?
    - 5.6448MHz : 128fs / 8.4672MHz : 192fs / 11.2896MHz : 256fs / 16.9344MHZ : 384fs / 22.5792MHZ : 512fs

    3. Meaning 32, 48, 64 in Page on the Table 3
    - are these data bit? 16bitx2(L / R) = 32, 24bit x 2(L/R) = 48, 32bitx2(L/R) = 64
    - If above is right, is this device support bit range 16 ~ 32bit?

    4. Can you give me Design guide for Output LPF Filter?
    ===============================================================
    Thanks
  • Hi, Jin,

    Please refer to my answers below:

    1. The bulk capacitor in PVDD pin of our EVM was selected so it can be used with several power sources without having issues due noisy supplies. This capacitor is used to decouple low frequency noise from the power source. The value selection depends heavily on the power supply used in the end-system, Usually we recommend a 10 µF or greater capacitor placed near the audio amplifier.
    2. The calculations are correct.
    3. The values on Table 3 represents the acceptable SCLK frequencies, this determines the word size of the data stream, so your approach is correct. However, the device accepts a maximum data size of 24bits per channel. When SCLK is 64xFs, the DAP masks unused trailing data bit positions.
    4. You can refer to SLOA119b app note for guidelines on Class-D LC Filter design.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • Hi Diego

    Your asnwer for my questions are very helpful for designer.

    Thanks