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Weird digital output at SRC4192 Sampling Rate Converter

Other Parts Discussed in Thread: SRC4192, DIR9001

Hello,

I'm about to find a suitable ASRC for my actual project and I tried to implement the SRC4192.

Unfortunately I got a very annoying problem with this chip. The digital output is not a valid datastream. There are a lot of weird bits together with the real data.

So I tried to find the error but I finally gave up and decided to ask here.

My configuration is pretty standard. I get a 44,1kHz signal from a DIR9001 and want to give it to a ADAU1701 DSP chip with 192kHz. 

You can find the schematics attached to this post.

The strange thing is that this SRC4192 starts creating weird bits as soon as any signal is attached to the LRCKI pin. Even if you leave SDIN and BCKI open and just give a 44,1kHz Signal to LRCKI, the SDOUT starts streaming weird stuff.

First I thought it's maybe because of a wrong input data format or a bad RCKI clock but I double checked everything and the data from DIR9001 is perfect.

SRC4192 should run as output master mode in 128fs. But I got this problem even in both slave mode.

Attached you can find the schematics, the bitstream from input and output (you already see these strange bits between the audio data), another screenshot of a muted input with just the weired bits and additional screens from input and output LRCK and BCK.

So maybe you got a idea about this issue. It would help me a lot.

Thanks in advance.

Yellow: DATA Input of SRC4192
Green: DATA Output of SRC4192 (you already see that this is not a valid I2S bitstream)

Yellow: DATA Input of SRC4192 (source muted)
Green: DATA Output of SRC4192 (weird bits at the output, it must be a all zero because of no input)

Yellow: LRCK Input of SRC4192
Green: LRCK Output of SRC4192 (Looks ok, 44k1 to 192k)

Yellow: BCK Input of SRC4192
Green: BCK Output of SRC4192 (Looks also good, 2.82MHz to 12.288MHz)

  • Hi Bernhard,

    Can you probe the RDY pin to see what its behavior is? We recommend that the RDY pin be tied to MUTE, so that when the ASRC is not valid, the part is muted. Is there correct output when the input clocks and data are good?

    Justin
  • Hi Justin,

    thank you for your reply. I already checked RDY, it goes high when the clocks at the input as well as the RCKI clock are valid. But I can probe it again and post a screen. Tieing RDY to MUTE will not help in my case unfortunately.

    The output is also that weird when there is a valid datastream at the input. You can see it on my first screen I posted. yellow is valid I2S stream and output is something strange (green line).

    I even checked if the input is really valid. I gave it to another device which accepted the data and played music.

    Do you have another idea? Maybe it's the chip itself... I already replaced it but you never know. The chips I got are already stored for some years....

  • Hi Bernhard,

    Since the part is up sampling the audio there will be an estimation of each individual sample and a delay, are you adding any type of delay to your comparison? Is it possible to compare the output of the DIR and the SRC in some audio test equipment such as an Audio Precision? It is hard to compare digital audio passing through a system by just looking at a scope shot. When Up sampling the SRC must add more samples than are present requiring it to estimate the exact sample amplitude to be between one sample and the next that is input. This could be why when there is no input, it still toggles the output, but in reality is a small change in the output.

    Justin
  • Hi Justin,

    thanks for your reply. It works now and you are right, the output toggles are normal at this device. I never saw it before so it confused me.
    After fixing a timing error at the ADAU1701 DSP chip the audio bitstream was accepted and well working.

    So thanks for your help.
    Best regards from germany.
    Bernhard