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TLV320AIC3105 - PGA gain not modified

JPC
Prodigy 30 points
Other Parts Discussed in Thread: TLV320AIC3105

Hello

I'm working on testbench with TLV320AIC3105 and SAMA5D3 evaluation board.

I define the audio path following:

MIC1R => Input Mix => Right PGA => Output Mix => LEFT_LO output

The data register used for this are:

Register: 01h  Data: 80"  Reset soft
Register: 16h  Data: 04"  MIC1R => PGA_R with 0dB attenuation
Register: 54h  Data: A3"  PGA_R => LEFT_LO with Volume -17.5dB to compensate external gains
Register: 10h  Data: 00"  PGA_R with 0dB gain
Register: 56h  Data: 0B"  LEFT_LO Active with 0dB gain

Operation is mysterious.
The input attenuator (16h), volume for output (54h) and the output gain (56h) change value well according to the writing in the registers.
But it is impossible to modify the PGA gain (10h) by writing in the register. The gain stay fixed. The reading of this register gives me the written value.

However, this script working properly on TI TLV320AIC3105 EVM !? The PGA can be modified without problem.
I did not find a notable difference between my testbench and EVM for Codec schematic part.
I tested several software and hardware (for exemple, I2C bus signals are correct) possibilities  without significant succes.
I have no more ideas.

Thank you in advance for your support.

  • 0
    TI__Guru* 84915 points
    Hello,

    Welcome to E2E and thank you for your interest in our products.

    Excuse me, could you provide more information about this issue? Are the I2S lines enabled (WCLK, BCLK)? Also, could you try powering up the ADC even if the DOUT pin will not be used?

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 30 points
    Hello,

    First of all, thank you for your quick reply.

    First point
    Actually, I2S interface is not used, reserved for future application. So, its state is that defined by the reset soft.

    Second point
    ADC powering up
    I am not sure to have understood your request.
    For me, register 16h with data 04h, D2 is 1, => Right ADC channel is powered up. Reading register 24h (ADC flag register) give me 04h, D2 is 1 => Right ADC is in power-up state.
    Unfortunatly, problem persists.

    Best regards
  • 0 in reply to JPC
    TI__Guru* 84915 points
    Hello,

    I tested your configuration on the EVM and it seems that all is in order until I enable the ADC. When the ADC is powered on, the PGA doesn't affect the gain of the output signal. So, make sure that the Right ADC (Page 0 / Register 22 / Bit D2) and Left ADC (Page 0 / Register 19 / Bit D2) are disabled.

    Please let me know if you have more questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 30 points

    Hello
    Thank you for your answer.
    Friday, I carried out other tests and arrived at the same conclusion as you.
    On the other hand, it does not seem normal to have to inhibit the ADC to use the PGA. Because in this case, how to make to get out digital data on the SPI bus for example?
    My interpretation is the following one.
    Documentation available on the site TI (SLAS513C - FEBRUARY 2007 - REVISED DECEMBER 2014) comprises an error, the bit D2 is defined as follows:
             0: Right ADC Chanel is powered down.
             1: Right ADC Chanel is powered up.
    The error is that the value of D2 is reversed, it would be necessary to have:
             0: Right ADC Chanel is powered up.
             1: Right ADC Chanel is powered down.
    There is also an error for bits D6-D3 with 1111: LINE1R is not connected to the left-ADC PGA. But it's not the left PGA for the register 22.
    Now, why don't I have this problem on EVM?
    In fact, whatever the value from D2, 0 or 1, the ADC is validated. I suppose that my EVM is equipped with an old version with the codec, and that an evolution of the product consisted in being able to program the ADC ON/OFF.
    The version of the EVM which I use is:
    6487972 BOM REV B
    6487975 BOM REV A
    You say that on your EVM to observe the same result as on my testbench. That wants to say that the EVM are now equipped with the last version with the codec.
    Best regards¶

  • 0 in reply to JPC
    TI__Guru* 84915 points
    Hello,

    I would mean that the ADC must be enabled in order to use the PGA_R => LEFT_LO path. The PGA can be only applied when the ADC is in use. Also, BCLK and WCLK signals must be applied correctly for a correct behavior of the ADC.

    Best regards,
    Luis Fernando Rodríguez S.