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TAS5760L clock error

Rogerio Rilhas
Prodigy 70 points
Other Parts Discussed in Thread: TAS5760L, TAS5760M

Hi,

I'm using a TAS5760L in 48 KHz 16-bit mono PBTL, but I'm getting a clock error (and no output at all), and I don't know what the reason for that may be.

I don't have a separate MCLK, so I'm using MCLK=SCLK, at 64fs, in I2S format.

I've observed the signals and they all look good. I even manually counted the relation between LCLK and SCLK, and confirmed that there are exactly 64 SCLKs for every LRCK.

I also checked the polarity of SCLK, to confirm that the LRCK and SDIN are changed on the negative transition so that they are stable on the positive transition.

I also confirmed the format manually, verifying that there is a dummy data bit right after the LRCK transitions, so I don't think I'm doing anything wrong with the format.

So, looking for other causes, I'm shutting down the amp, starting clocks, muting, taking the amp out of shutdown, un-muting, and then playing a short speech sample (from 0.9 seconds to 1.7 seconds). Could it be that the amp needs more time to accept the clocks and the speech is too short? If so: how much time does it need?

Another thing is that I'm not producing exactly 48 KHz (64fs=3.072 MHz), the actual frequency is roughly 47.5 KHz (64fs=3.040 MHz). Could this be the reason for the amp to report clock errors? If so, how close to 48 KHz will it need to be?

The datasheet provides no insight into what the actual cause of the clock error may be, so I don't know what else to look for.

Another thing: the SPK_GAIN[1:0] lines are set to 11(b) after the amp is powered up (by a microcontroller that needs some time to startup). The first shutdown of the amp also happens some time after power up (shutdown is set by the same microcontroller after the code starts to run). The datasheet is very clear about the I2C address being sampled when the amp powers up, but it is not that clear about when the SPK_GAIN[1:0] values are sampled. Could this be the source of the problem?

Below are the register values I'm reading from the amp (I'm setting them - except ID and fault registers - but then also reading them back to confirm they were correctly received by the amp):

Reg00ID = 00000000 = 0x00 (the datasheet says it should be 0x00 in some places, and 0x01 in other places)

Reg01Power = 11111101 = 0xFD

Reg02Digital = 00010100 = 0x14

Reg03Volume = 10000000 = 0x80 (starts with 0x83 for muting, and then I change it to 0x80 for playing)

Reg04VolL = 11001111 = 0xCF

Reg05VolR = 11001111 = 0xCF

Reg06Analog = 11010011 = 0xD3 (PBTL from left channel)

Reg08Errors = 00011000 = 0x18 (starts with 0x08 at first power up, and after 10 or 20 minutes of operation switches to 0x18)

Is there anything else I can do to find the cause? Or to try and figure out a solution to the problem? Any hidden "debug" register I can read, or something else I can try?

Thanks!

PS: The datasheet I used for the implementation is "SLOS782B –JULY 2013–REVISED SEPTEMBER 2015".

PS2: I have a 6 ohm loudspeaker connected to the amp (through a circuit similar to the one described in the datasheet).

  • 0
    TI__Guru 57800 points

    Hi, Rogerio,

    Welcome to E2E, Thanks for your interest in our products!.

    The TAS5760L has the capability of using the same signal to drive MCLK and BCLK when SCLK is running at 64xFs with 44.1KHz or 48KHz sampling Frequency. However, I think that as your sampling rate is not 48KHz, the device is detecting that LRCLK is running at unsupported rate.

    Have you tried using different I2S signals to verify if the clocks are causing the issue?, 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 70 points
    Hi,

    Thanks for your quick reply.

    The datasheet is not clear about how accurate the sampling rate should be, it just says that fs should be between 32 KHz and 96 KHz. So, I assumed that 47.5 KHz would be a fairly decent approximation to 48 KHz, and well within the specified range. So, assuming that I won't ever be able to produce a sampling frequency of exactly 48000.0000000000000 Hz, what range around 48 KHz will the amp accept?

    Yes, I tried an I2S signal with all zeroes, one with a hardcoded 0xafaa (so that I could check the signals manually), and also actual sample data (mono only). I think that the special case of a signal with all zeroes is very informative, as in that case there are only 2 actual signals (SCLK=MCLK, and LRCK), but the amp still indicates a fault (at the fault pin) and a clock error (in the fault register).

    I also tried setting the PBTL source to the right channel instead of the left channel, but the result was the same.
  • 0 in reply to Rogerio Rilhas
    TI__Guru 57800 points

    Hi, Rogerio,

    My suggestion was more focused to use an external I2S source (Like our PurePath Console Motherboard) connected to the TAS5760M I2S inputs. This way you can verify that the issue is related to the I2S clocks.

    As you can see in Table 1. Protection Suite Error Handling Summary,  the device should return to normal operation once the I2S clocks returns to valid state.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 70 points

    Hi,

    Thanks for your suggestion.

    However, in this particular instance I can't go with a trial-and-error solution, and I would rather have exact specifications to follow and to prepare for (like a requirement on the accuracy of a 48 KHz sampling frequency, for example), otherwise I'm not able to assure my clients that they will have the project ready in time and working as expected.

    Also, I usually don't have the opportunity to experiment with development kits before making a commitment to my clients, but in this case I just assumed that the amplifier would accept a clock "reasonably" close to 48 KHz (as other I2S devices I used in the past do), and I'm starting to believe that I made a mistake in trusting that the "32 KHz to 96 KHz" specification gave me the freedom to have a 1% error in the 48 KHz sample clock.

    I think that an error flag indicating "clock error" is simply not enough. Furthermore, I think it is a bad design option to have the amp shutdown when the clock has a 1% error, and I think the amp should keep on playing in case of such errors, allowing the microcontroller to decide whether or not to stop audio when faced with such situations. Having the amp not play simply kills all audio in my project, and I don't even have the option of having "acceptable audio" working.

    This project is not a long 1-year project, so I don't have the time to make revisions of the board or experiments in the 1-month from specification to delivery, so it is important that components don't behave in unspecified and undocumented ways, and whatever behavior is not specified should simply work. Even taking 1 day to wire some other source into the board represents a terrible waste of resources, just to find out some parameter that is not mentioned in the datasheet (assuming that I can find the error, of course). Then fixing it is probably another problem, requiring a new board, a new design, and possibly another microcontroller (the one I'm using can't get closer than 1%).

    But, most importantly, not knowing how close to 48 KHz the clock needs to be is a major show stopper, and if that turns out to be the problem in this case then I think it is a very serious error on TI's part to not have provided enough information about it in the datasheet.

    Anyway, thanks for your help.

  • 0 in reply to Diego Melendez
    Prodigy 70 points
    Hello again,

    Before giving up on the TAS5760L I decided to try it in hardware mode (which is something I can do with the current PCB I have), and I got a curious result.

    So, shutting down, setting FREQ/SDA=0 (16x), PBTL/SCL=1 (PBTL), SPK_GAIN[0:1]=00 (hardware mode), starting the clocks (MCLK=SCLK=64xLRCK=47.5KHz), waiting 500ms, and then releasing from shutdown, results in the fault pin going low for 10us, and then high for about 350us, apparently repeating continuously.

    Does this provide any new clue about what the problem may be? Can it still be the 1% difference from 47.5 KHz to 48 KHz in the clocks?

    I also assembled a second (equal) PCB and the problem is the same (either in hardware of software control mode), so I ruled out any fault with a specific amp chip.
  • 0 in reply to Rogerio Rilhas
    Intellectual 310 points

    I am curios did you resolve this issue?

    I am working with this part now and cannot get past CLK Error (Bit3), Fault_Configuration_and_Error_Status register @ address [0x08] 

    Have tried many combinations of MCLK, SCLK, LRCLK.

    I note your comments about clock accuracy, my micro controller is also a little out on frequency generation but i wouldn't expect it to be an issue if all of the clocks track together.

    Have you found a clock rate that works ?

    Any light you can shed would be appreciated.

    Rob

  • 0 in reply to Rob Price
    Prodigy 70 points
    Hi,

    No, I haven't resolved the problem, I tried everything I could with MCLK=SCLK=64fs, and it didn't work, and I had 2 boards so I think it is very unlikely that the problem was faulty units, or some other hardware issue with my boards.

    However, I did get it working by separately driving MCLK=128fs and SCLK=64fs, and as soon as I did that the amplifier started working immediately. After that, varying the sampling frequency widely around the 48KHz target didn't have any effect on the operation of the amplifier, so my guess is that the problem was never a lack of accuracy of the sampling rate.

    My conclusion is that the datasheet is plain wrong, and you can't get the amplifier working at fs=48KHz by setting MCLK=SCLK. I was fortunate enough to be able to separate MCLK and SCLK in my boards, because I have some experience that TI's datasheets can be really bad, and are sometimes riddled with incorrections and omissions, so for me it has always been good idea to have a backup plan whenever I some TI's chip for the first time. In this case, designing a board where I could separate MCLK from SCLK if I ever needed to proved to be invaluable to the success of the project. It didn't save me from a terrible waste of time trying to figure it out, though.

    I wish you the best of luck.