TLV320AIC3104 - Implications for not using MCLK as source for internal master clock

Arun Sivakumaran

Other Parts Discussed in Thread: TLV320AIC3104

Hello,

We have a beaglebone black reference design based embedded platform on which we are planning to integrate the TLV320AIC3104 for basic audio playback and recording (we are not looking for any hi fidelity use case). We are using the beaglebone audio cape as a reference for our integration - elinux.org/CircuitCo:Audio_Cape_RevB

Because our embedded platform already is using GPIO3_21 for another purpose, we would like to use BCLK instead as a master clock source for the codec chip. From the datasheet, I gather that this is possible and that we should stick to 16-bit or 32-bit data width cases to avoid jitter issues.

What we would like to know is:

1. Is there any implication / downside to using BCLK instead of MCLK as the internal audio master clock source?

2. Is there a use case / application note that you could point me to, if one is available or that you know of, where BCLK is used as master clock source, that would help in our bring up effort

3. For software changes, other than changing the clock source to BCLK in the tlv320aic3x codec driver, does anything else need to be changed?

thanks,

Arun

over 9 years ago

0 Luis Fernando Rodriguez S. over 9 years ago

TI__Guru* 84915 points

Hi, Arun,

1. There's no difference between BCLK and MCLK if it is used as internal audio master clock source. It is just a different path which will be used for the ADC/DAC sampling frequency generation.

2. We don't have an application note where the BCLK is used as master clock source. However, take a look at the following script. It is an example of playback mode using the BCLK as master clock source.

Fullscreen BCLK_CLK_INPUT.txt Download

# BCLK = 2.8224MHz; WCLK = 44.1kHz

# Page 0
w 30 00 00
#
# Software reset
w 30 01 80
#
# Clock Generation Control
w 30 66 22
#
# PLL Programming
w 30 03 11 40 00 00
#
# Audio Codec Overflow (R value)
w 30 0B 02
#
# Clock Register
w 30 65 00
#
# Codec Data-Path Setup
w 30 07 8A
#
# DAC Power and Output Power Control
w 30 25 C0
#
# DAC Output Switching Control
w 30 29 02
#
# Left-DAC Digital Volume Control
w 30 2B 00
#
# DAC_L1 to LEFT_LOP/M
w 30 52 80
#
# DAC_R1 to RIGHT_LOP/M
w 30 5C 80
#
# LEFT_LOP/M Output Level
w 30 56 09
#
# RIGHT_LOP/M Output Level
w 30 5D 09

3. You only must ensure that the clock dividers are adjusted to the BCLK frequency to reach the correct sampling frequency. The rest of the codec configuration is the same.

Best regards,
Luis Fernando Rodríguez S.

0 Arun Sivakumaran over 9 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 180 points

Hi Luis,

Thanks for such a quick response as well as the excellent pointers!

This will certainly help us with our integration effort.

kind regards,
Arun

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TLV320AIC3104 - Implications for not using MCLK as source for internal master clock