TLV320AIC14K reference design

Hi, Jorge Miguel,

You may find information about our evaluation module on the TLV320AIC14KEVM User's Guide. 

Could you provide some information about your application? I will search for more information about the gerbers.

Best regards,
Luis Fernando Rodríguez S.

Hello,

Regarding the design of a 16 cascaded CODEC SMART TDM, I have one doubt.

I can see on the datasheet that all CODECs must be reset before the Automatic Cascade Detection (ACD). I understand that after powering up all devices must be reset at the same time.

However I wonder if resetting only one device makes sense. What is the behavior of the SMART TDM bus when only one out of the 16 CODECs is reset? Is the SMART TDM broken and all CODECs must be simultaneously reset in order to initiate the ACD again?

I interface the SMARTTDM bus with an FPGA and I wonder if an individual reset line for each CODEC makes sense or just one reset-line for all of them is enough.

Many thanks in advance,
Jorge

Hi, Jorge,

The ACD operation starts when the reset is applied. The ACD requires 132 MCLK pulses after reset to complete the operation. These pulses determine the number of devices and the relative position on the chain. So, we suggest to apply the reset to all the codecs in the chain to ensure that all the devices are working and synchronized correctly. We cannot guarantee that the individual reset will work.

Best regards,
Luis Fernando Rodríguez S.

Hi,

I will have a 16 chain CODEC configuration. Following your guidelines I will apply a synchronized RESET to all CODECs in order to trigger the ACD procedure.

After the ACD process every CODEC will have an address as indicated in "Table 1. SMARTDM Device Addresses" on the datasheet.

My question: Is the I2C interface ready in each CODEC just after the ACD?

On page 27:

“The host port uses a 2-wire serial interface (SCL, SDA) to program the AIC1x's six control registers and selectable protocol between S2C mode and I2C mode. The S2C is a write-only mode and the I2C is a read-write mode selected by setting the bits D1 and D0 of control register 2 to 00 or 01.”

Does it mean that a write on control register 2 must be made through DIN interface before the I2C interface is ready?

I just need to capture 16 analogue channels so I only plan to read DOUT without sending anything through DIN. I could do that if after the ACD the I2C interface is ready but reading the datasheet it is unclear for me.

Many thanks,

Jorge.

Hello Luis Fernando,

I am testing my first board with 16 cascaded CODECs.

I am able to read and write to all CODEC. That means they have successfully self-discovered.

However I am having troubles when configuring their parameters:

- With broadcast I2C frames, I try to configure:

a) Continuous mode

b) 8 KHz sampling rate

After the corresponding I2C frames, I can see that the clock is not continuous, it is a burst clock. Between two FS master signals, there are 16 SCLK burst each of them of 11 clocks (that is strange). Is turbo operation what I am seeing? But only 11 SCLK on each burst I find it weird. 

I saw that default mode is standard operation (REG 2) but writing a 0 on D7 (turbo=0) does not change anything.

Furthermore, the formlula: FS=MCLK/(16xMxNxP) does not work for me.

If P=8, the desired FS should be

FS=12288KHz / (16 x M x N x P=8). If M=3 and N=4 I should get 8KHz. However I only get 2KHz

Do you have any hint on what I am doing wrong?

Many thanks in advance

Jorge

Hello, Jorge,

In cases where the FS is not the expected one, there could be mistakes in register configuration number 4 or even in the conditions that should be taken.

When P is configured as 4, the device enters in coarse sampling frequency (default mode). You must ensure that all the steps of Operating Frequencies section are being followed. Also, ensure that the register 4 notes are being followed correctly:

- It takes 2 sampling periods to update new values of M, N and P.
- FSDIV must be configured as FSDIV = 1 to modify M and FSDIV = 0 to modify N and P.

Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

Hello Luis Fernando,

It seems I can also control the SCLK frequency. For continuous mode, it is necessary to set D0 of register 1 to '1'. It was not clear to me that procedure. Now I think that I control the frequency sample and the SCLK frequency without problems.

The burst MCLK was probably due to reflections between the master and the other 14 slaves. Now I think it is solved and MCLK is a "continuous" clock. And I write "" because I have an issue:

SCLK and FS are clock inputs of one FPGA which captures the audio of the 16 CODECs. I am not able to see the real rising edge of these signals but apparently there are many bounces that cause my FPGA to be triggered several times on each rising edge. I think it is due to reflections of those signals since the SCLK of the master goes to SCLK of the other 14 CODECs and the FPGA. I designed that trace with a series resistor at the output of the SCLK master but the problem does not go away. My configuration is a tree from the master to the slaves with each line equalized so that every device sees the rising edge at the same time.

Is there any rule to design this kind of connections in order to avoid reflections?

Many thanks in advance

Regards,

Jorge

Hi, Jorge,

We only have recommended layout connections in order to prevent possible noise from digital side to analog side. This is related with the digital and analog ground planes. These planes must be separated and joined in one point. Also, another possible layout (in case that this is not possible) is to surround the digital lines with a ground plane. This will ensure that all the digital activity won't affect the rest of the lines.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis Fernando,

Yes I followed all your recommendatios regarding digital and analog ground planes. The problem is clock distribution. Anyway with careful in the FPGA can be solved.

Now I have an important question. What format does the 16 digital bits that outputs the ADC?
They are 16 bits lineal, but what format do they have?
- 16 bits without sign
- 16 bits plus sign (meaning MSB is the sign and 15bits left the amplitude value)
- twos compliment

It is not specified on the documentation and I do not know how to process the data.

Thanks in advance.

Regards,
Jorge

Hi, Jorge,

The TLV320AIC14K data format is 2's complement signed. This is the data format in the most part of our codec devices.

Best regards,
Luis Fernando Rodríguez S.

Hello Luis Fernando,

Due to the footprint, I changed to TLV320AIC12K, which is supposed to be the same but adding analogue outputs.

Since the datasheet of both of them is the same document, I assume that TLV32012K digital output is also 2's compliment signed?

Where is that information on the datasheet? I can't find it.

Hello, Jorge,

It is also 2's complement Data Format. Actually, it is only specified in Features section of datasheet (first page).

Best regards,
Luis Fernando Rodríguez S.

Luis Fernando,

Thanks for the two compliment confirmation.

One more question. In my system there are many IC's acting like CODECs and one acting like DECODEC. I switch from any CODEC source to the DECODEC sink. My problem is that the DECODEC is most of the time initializes in the wrong way. The analogue audio output is distorted.

The source CODECs (16 cascade master-slave) are initialized with FPGA1 and DECODEC (stand-alone master) with FPGA2

I tested that with a 1KHz analogue signal and I have to initialize the DECODEC several times in order to see the 1Khz tone at the analogue output. It seems to be random.

The way I initialize the DECODEC is:

- Continuous MCLK at 12288MHz

- Reset HW at RESET input: at least 6 clock long

- Wait at least 132 clocks

- Write in I2C:

-- 0x10 at register 4: set N and P

-- 0x06 at register 4: set M

-- 0x41 at register 1: set continuous mode of operation

-- 0x10 at register 6: set OUTP3=ON.

At the analogue output, I can see the 1KHz tone and 3Khz and 2 KHz tones. I assume that it is distortion as if the DECODEC was saturated. By keeping the CODEC sources without changes (FPGA1 does not reset the CODECs), I apply the initialization routine at the DECODEC (FPGA2) several times (random number) until the analogue output is just the 1HHz tone, without harmonics.

Is there anything missing in the initialization routine?

Many thanks for your very useful help,

Regards,

Hi, Jorge,

These results make me think that this could be related with a marginal configuration (probably due to a initialization timing). Could you add a delay of 10 clock pulses after register 4 is initialized? Also, could you add the same delay after the continuous mode is configured?

Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis Fernando,

I have added delays after each I2C frames. However problem does not go away. 

Even reading the registers gives me correct values:

Reg1: {0x61}

Reg2: {0x20}

Reg3: {0x11}

Reg4: {0x86}{0x10} (FS=8KHz given MCLK=12288KHz).

Reg6:{0x10} (OUTP3=ON)

It is still sometimes (randomly) initiated at very high volume and very distorted. I even decrease the default gain of DAC from 0x2A to 0x1A but no change.

Have you ever experienced something similar?

Many thanks,

Jorge

Hi, Jorge,

Have you tried waiting more clock cycles after the hardware RESET is applied? Normally, you should wait at least 132 clocks. Could you increase the number of clocks to see if it improves?

Best regards,
Luis Fernando Rodríguez S.