• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 647 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How to generate the adc and dac sample rates by using BCLK3 and WCK3?

venkat ediga
Intellectual 490 points
Other Parts Discussed in Thread: TLV320AIC3262

HI,

I want generate the  sampling rates by using the BLCK3 and WCLK3.

I referred the TLV320AIC3262 datasheet, 2.7.2 Low Frequency Reference Clock.

1)get the clocks from host to codec is wclk=48 kHz and bclk=1.536 MHz.

2)According to datasheet  LFR_CLKIN should be less than 50 KHZ.

3.here i can't  use the bclk,if can use the wclk(48 kHz)  then how it will work.

4. wclk is  directly goes to LFR_CLKIN,LFR_CLKIN should connected to Clock Frequency Multiplier,there what about the MCLK1 and HF_OSC_CLK.

5.here MCLK1 is required,if i can use the wclk.

6.i used wclk(48 KHZ),then what is the value of HF_REF_CLK.

7.please give me the solution for above lines and  explain how to use the ASI3 slave mode.

8.please share me any code base for ASI3 slave mode  with LFR_CLKIN configurations.

Thanks