Our design needs TLV320AIC22C chip.
But TLV320AIC22C is not recommended for new designs.
Can you suggest a chip which is equivalent to TLV320AIC22C and is active now?
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Our design needs TLV320AIC22C chip.
But TLV320AIC22C is not recommended for new designs.
Can you suggest a chip which is equivalent to TLV320AIC22C and is active now?
Hi, Sita,
Please take a look at the TLV320AIC1110 and TLV320AIC1103. These are PCM codecs that support 15-bit linear data and 8-bit companded (u-law and a-law) data. Please let me know if you have more questions or comments.
Best regards,
Luis Fernando Rodríguez S.
Hi Rodriguez,
In TLV320AIC2x:
The control mechanism implemented through SCLK, FS, DIN and DOUT for reading and writing data has to be implemented in the Microcontroller also, which will use up much of the processing power of the microcontroller(because the control mechanism is not a standard protocol like SPI, I2C etc).
TLV320AIC1110 also has a similar implementation with PCMIN, PCMSYN, PCMCLK, PCMOUT
Please suggest an alternative design for sending and receiving the PCM data to/from the codec chip.
Regards,
Sitaramaraju Chiluvuri
Hi Rodríguez,
In the data sheet of TLV320AIC1110, data transmission happens through pins PCMCLK, PCMSYNC, PCMI, PCMO. I watched the data transfer timing diagrams(Figure 4 and figure 5 for 128khz), but could not understand it completely.
Questions:
1. At every high to low transition of the PCMCLK, data is clocked into PCMI, and clocked out of PCMO. Am I right in my understanding?
2. What protocol is it? (I2S, left/right justified, etc). With this answer I can find out whether Application-Report-slaa449a is mostly valid for data transmission in TLV320AIC1110
Regards,
Sitaramaraju Chiluvuri
Hi, Sitaramaraju,
The TLV320AIC1110 has its own PCM protocols that are little different from the I2S, DSP and left/right justified modes. The differences are in the point where the data is sent or taken. In case of the protocol at 128kHz, the data is sent/taken at the falling edge of the PCMCLK after the rising edge of PCMSYNC. In case of the diagram at 2.048MHz, the data is sent/taken at the falling edge after the PCMSYN pulse.
These modes are related with the left-justified and DSP modes (see the TLV320AIC3104 datasheet for more details about these protocols). Due to these differences, these modes are called PCM modes.
Please let me know if you have more questions or comments.
Best regards,
Luis Fernando Rodríguez S.