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AIC3254 in slave mode how to setting the Divider

Dear Sir,


IWe us AIC3254 for Slave mode, MCLK = 11.288MHz, BCLK = 1.411MHz, LRCLK = 44.1KHz,
How to setting the PLL?
The BCLK must 64*LRCLK?

  • Hi, 

    For this case, there're no possible PLL values to get an exacly LRCLK = 44.1KHz with MCLK = 11.288MHz. The PLL that you may use to approach the desired frequency would be:

    P = 1; R = 1; J = 7; D = 5011; N = 3; M = 5 and AOSR = 128.

    I suggest to use another MCLK frequency such 11.2896MHz. This MCLK value only needs the dividers to get the LRCLK frequency:

    N = 1; M = 2; AOSR = 128.

    Please let me know if you have more questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.