After confirming that the control signals, /RESET, /PDN, etc are not asserted, and you are able to correctly write IIC commands, read Register x02, the Error Status Register.
The Error Status Register is a "sticky" register which means that it is not cleared after device initialization; therefore, you must write x00 to it and wait for a few milliseconds before reading it, the first time. The information contained in this register will inform you if are clocking errors (that is generally the case). You can then refer to the timing diagrams in the datasheet to understand the timing ISS relationship and make corrections.
HINT: Continually reading the Error Status Register (x02) is a good technique to use during system validation.
NOTES:
All digital audio clocks must be synchronous.
MCLK phase and polarity are not critical, as long as it is synchronous.
Keep the connections of the digital bus short and do not run them through a cable (IIS is a "short haul" connection).