Hello everyone,
I'm facing difficulties to used my codec without the MCLK, i'm tring to configure the PLL with BCLK. And i used the PLL configuration from the Table 2-27. PLL Example Configurations of the datasheet : P=1, R=3,J=10,D=0, MADC=3,NADC=5,AOSR=128, MADC=3, nDAC=5 , DOSR = 128 .
I want to realize a playback from i2s to line output and HP and recording from IN2 to i2s.
this is the codec configuration i used :
/*********************************************** * Software Reset **********************************************/ /* Select Page 0 */ Codec_WriteRegister(PAGE_SELECT,0x00); /* Initialize the device through software reset*/ /* Carry out the software reset */ Codec_WriteRegister(RESET_CODEC,0x01); delay_ms(10); // wait 10ms after reset /**********************************************/ /*********************************************** * Clock Settings * --------------------------------------------- * The codec receives: MCLK = 0 MHz, * BLCK = 2.8224 MHz, WCLK = 44.1 kHz *********************************************** * Select Page 0*/ Codec_WriteRegister(PAGE_SELECT,0x00); /* PLL */ /* PLL is CODEC_CLKIN register 4*/ // MCKL is input to PLL // PLL clock is codec_clkin Codec_WriteRegister(CLK_REG_1,0x07); /* PLL divider R =1 * PLL divider P =3 * PLL power up*/ Codec_WriteRegister(CLK_REG_2,0x93); /* PLL divider J = 10 */ Codec_WriteRegister(CLK_REG_3,0x0A); /* 0x0B Clock Setting Register 6, NDAC Values * NDAC = 1, MDAC = 2*/ //w 0b 81 82 Codec_WriteRegister(NDAC_CLK_REG_6, 0x85); Codec_WriteRegister(MDAC_CLK_REG_7, 0x83); /* 0x12 Clock Setting Register 8, NADC Values * NADC = 1, MADC = 2 w 12 81 82 */ Codec_WriteRegister(NADC_CLK_REG_8, 0x85); Codec_WriteRegister(MADC_CLK_REG_9, 0x83); /* Configure audio interface*/ //w 30 1B C0 Codec_WriteRegister(AIS_REG_1,0xC0); //Left justified I2S /***********************************************/ /*********************************************** * Signal Processing Settings ***********************************************/ /* Select Page 0*/ Codec_WriteRegister(PAGE_SELECT,0x00); /* Set the DAC Mode to PRB_P8 , w 3c 08 */ Codec_WriteRegister(DAC_SIG_PROC,0x08); /* Set the ADC Mode to PRB_P1 , w 30 3d 01 */ Codec_WriteRegister(ADC_SIG_PROC,0x01); /**********************************************/ /*********************************************** * Configure Power Supplies ***********************************************/ /* Select Page 1 */ Codec_WriteRegister(PAGE_SELECT,0x01); /* Power up AVDD LDO , w 30 02 A9 */ Codec_WriteRegister(LDO_CTL,0xA9); /* Disable weak AVDD in presence of external * AVDD supply ,w 30 01 08 */ Codec_WriteRegister(POW_CFG,0x08); /* Enable Master Analog Power Control * Power up AVDD LDO , w 30 02 A1*/ Codec_WriteRegister(LDO_CTL,0xA1); /* Set the input power-up time to 3.1ms (for ADC)*/ //w 30 47 32 Codec_WriteRegister(0x47,0x32); /* Set the REF charging time to 40ms*/ //w 30 7b 01 Codec_WriteRegister(0x7B,0x01); /***********************************************/ /*********************************************** * Playback/Recording Setup ***********************************************/ /* Select Page 1 */ Codec_WriteRegister(PAGE_SELECT,0x01); /* Route IN2L to LEFT_P with 20K input impedance*/ //w 34 20 Codec_WriteRegister(LMICPGA_PIN_CFG,20); /* Route CM1L to LEFT_M with 20K input impedance*/ //w 36 80 Codec_WriteRegister(LMICPGA_NIN_CFG,0x80); /* Route IN2R to RIGHT_P with 20K input impedance*/ //w 37 20 Codec_WriteRegister(RMICPGA_PIN_CFG,0x20); /* Route CM1R to RIGHT_M with 20K input impedance*/ //w 39 80 Codec_WriteRegister(RMICPGA_NIN_CFG,0x80); /* De-pop: 16 time constants, 6k resistance*/ //w 30 14 35 Codec_WriteRegister(HPHONE_STARTUP_CTRL,0x35); /* Route LDAC/RDAC to HPL/HPR*/ //w 0c 08 08 Codec_WriteRegister(HPL_ROUTE_CTL,0x08); Codec_WriteRegister(HPR_ROUTE_CTL,0x08); /* Route LDAC/RDAC to LOL/LOR*/ //w 0e 08 08 Codec_WriteRegister(LOL_ROUTE_CTL,0x08); Codec_WriteRegister(LOR_ROUTE_CTL,0x08); /* Power up HPL/HPR and LOL/LOR drivers*/ //w 09 3C Codec_WriteRegister(OUT_PWR_CTL,0x3C); /* Unmute Left MICPGA, Gain selection of 6dB to make channel gain 0dB * Register of 6dB with input impedance of 20K => Channel Gain of 0dB*/ //w 3b 0c Codec_WriteRegister(LMICPGA_VOL_CTRL,0x0C); /* Unmute Right MICPGA, Gain selection of 6dB to make channel gain 0dB * Register of 6dB with input impedance of 20K => Channel Gain of 0dB*/ //w 3c 0c Codec_WriteRegister(RMICPGA_VOL_CTRL,0x0C); /* Unmute HPL/HPR driver, 0dB Gain*/ //w 10 00 00 Codec_WriteRegister(HPL_GAIN,0x00); Codec_WriteRegister(HPR_GAIN,0x00); /* Unmute LOL/LOR driver, 0dB Gain*/ //w 12 00 00 Codec_WriteRegister(LOL_GAIN,0x00); Codec_WriteRegister(LOR_GAIN,0x00); /* Select Page 0*/ Codec_WriteRegister(PAGE_SELECT,0x00);; /* DAC => 0dB*/ //w 41 00 00 Codec_WriteRegister(LDAC_VOL,0x00); Codec_WriteRegister(RDAC_VOL,0x00); /* Power up LDAC/RDAC*/ //w 3f d6 Codec_WriteRegister(DAC_CHN_REG,0xD6); /* Power up LADC/RADC*/ //w 51 c0 Codec_WriteRegister(ADC_REG_1,0xC0); /* Unmute LDAC/RDAC*/ //w 40 00 Codec_WriteRegister(DAC_MUTE_CTRL_REG,0x00); /* Unmute LADC/RADC*/ //w 52 00 Codec_WriteRegister(ADC_FGA,0x00);
My problem is : i have no data on the DAC output.
But the is data on the i2s on both side.
Do you have an idea about the origin of the problem?
thanks
