TLV320AIC3101 _ SNR of ADC in double rate

KANJI SHIBATANI

Mastermind 6205 points

Other Parts Discussed in Thread: TLV320AIC3101

Hello

Please give me your advise about TLV320AIC3101 of SNR & clocking.

My customer is using TLV320AIC3101 for their portable-audio product many years.

So, My customer says that they found phenomenon.

If clocking using PLL enable, SNR of ADC at fs=88.2KHz/96KHz is fine.( ~ 92dB)

However, in case PLL desable, SNR is worsen ( ~86dB).

This is just for double rate only.

Also, this phenomenon does not occur in DAC portion.

I attached the pdf file for your reference.

Is this reasonable?

I would like to know your opinion/advise.

Best Regards

AIC3101_SNR_in double_rate.pdf

over 9 years ago

0 Luis Fernando Rodriguez S. over 9 years ago

TI__Guru* 84915 points

Shibatani-san,

I will search for more information about this. I will let you know if I find something related with this issue.

Best regards,
Luis Fernando Rodríguez S.

0 Luis Fernando Rodriguez S. over 9 years ago in reply to Luis Fernando Rodriguez S.

TI__Guru* 84915 points

Shibatani-san,

These are expected results. The double-rate mode reduces the SNR as you mentioned. This is due to certain conditions that must be taken when the double-rate mode is configured.

So, we recommend to use the PLL (blue path) this time, instead the clock divider (red path).

Please let me know if you have more questions or comments.

Best regards,
Luis Fernando Rodríguez S.

0 KANJI SHIBATANI over 9 years ago in reply to Luis Fernando Rodriguez S.

Mastermind 6205 points

Dear Luis san,

Thank you for your answer immediately !

Certain conditions in double rate-mode ( Q =4, 8, .. ) should be satisfied not only DAC but also ADC ?

( data sheet page 27 describes about DAC, but same thing as ADC ?)

http://www.tij.co.jp/jp/lit/ds/symlink/tlv320aic3101.pdf

0 Luis Fernando Rodriguez S. over 9 years ago in reply to KANJI SHIBATANI

TI__Guru* 84915 points

Shibatani-san,

That's correct. The effect of the Q value affects both sampling frequencies (ADC and DAC). So, the restrictions for the Q values should apply for both cases.

So, we recommend to use the PLL (blue path) this time, instead the clock divider (red path).

Best regards,
Luis Fernando Rodríguez S.

0 KANJI SHIBATANI over 9 years ago in reply to Luis Fernando Rodriguez S.

Mastermind 6205 points

Dear Luis san

Thank you for your answer quickly.

Please close this.

Thank you again.

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TLV320AIC3101 _ SNR of ADC in double rate