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TLV320AIC3101 clock setting violation

KANJI SHIBATANI
Mastermind 6205 points


 

Hello

My customer found that their mistake about clock setting for their product in the market.

 

~~~~~

Customer's setting

fs(ref)＝(PLL_CLKIN×K×R)/（2048×P）

K=J.D＝1.0

R=8

P=2

PLL_CLKIN=512×fs(ref)

fs(ref)＝44.1k/48kHz

~~~~~

Customer had missed ( violate) the condition 4< J <11 !! Customer had already

shipped  using this setting in the market and they have concern.

 

**Question**

What kind of pheneomenon may be  occur if violate  J >4.

For exmaple SNR is worsen, PLL is unstable and tolerance of fs(ref) worsen, etc..

 

Best Regards

  • 0
    TI__Guru* 84915 points
    Shibatani-san,

    When the PLL coefficients ranges are not respected, there's risk to have less performance in the signal quality. In some cases the signal is not affected and the quality is the same. However, there could be some distortion in other cases. If the PLL conditions are satisfied, the sampling rate is achieved correctly and the signal performance is as expected.

    Best regards,
    Luis Fernando Rodríguez S.