TLV320DAC3203 overflow problem

Hi, Cyril,

Welcome to E2E and thank you for your interest in our products!

The overflow is caused when the sent data is greater than the maximum allowed. Depending on the configured word length, the DAC can allow a determined range. For example, if the word length is configured as 16-bits, the allowed range would be 0x8000 to 0x7FFF. Please make sure that the PCM file values are in the correct range.

Please let me know if you have more questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Thank you for your reply,

What kind of PCM files the DAC is supposed to read with a 16-bits word length configuration? I didn't find anything in the documentation about the PCM. Is it signed ?
How could it overflowed when the DAC simply takes the value within the range of the word length?

Regards,
Cyril

Hi, Cyril,

The TLV320DAC3203 data format is 2's complement signed. Also, the overflow can be due to a high gain/volume in the device. Could you provide your entire register configuration to have a better approach to this issue?

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

Knowing that I want to use LDOIN supply with LDOIN 3.3v
IOVdd is also 3.3v, Dvdd is 1.8v and a set of two capacitor is put between Avdd and Avss.

Here is the register configuration:

#----------- Initialize to page 0
w 30 00 00
#----------- Initialize the device through software reset
w 30 01 01
#----------- Power up pll, set pll divider P=2 and pll divider R=1,
w 30 05 A1
#----------- Set pll divider J=8
w 30 06 08
#----------- Set pll divider D=4672
w 30 07 12
#---------- part 2
w 30 08 40
#----------- Power up and set NADC divider = 5,
w 30 0b 85
#----------- Power up and set MDAC divider = 4
w 30 0c 84
#----------- Set DOSR = 120
w 30 0d 00
#---------- part 2
w 30 0e 78
#----------- Set the DAC mode to PRB_P25 to produce beep
w 30 3c 19
#----------- Set the audio interface : Type : I2S; word lenght 16 bits; bclk output; wclk output
w 30 1b 0C
#----------- Set Bclk and Wclk on even when dac powered down
w 30 1D 04
#----------- Set Bclk divider to 3
w 30 1e 83
#----------- Set PLL_CLKIN as MCLK and CODEC_CLKIN as PLL_CLK,
w 30 04 03
#----------- Select page 1
w 30 00 01
#----------- Set the REF charging time to 40ms
w 30 7b 01
#----------- Enable analog blocks
w 30 02 01
#----------- Set the input common mode to 0.9V and output powered by LDOIN
w 30 0a 33
#----------- Route left DAC to HPL
w 30 0c 08
#----------- Route right DAC to HPR
w 30 0d 08
#----------- Set the DAC PTM mode to PTM_P1
w 30 03 08
#---------- part 2
w 30 04 08
#----------- Set the HPL gain to 0dB
w 30 10 00
#----------- Set the HPR gain to 0dB
w 30 11 00
#----------- HP soft stepping settings for optimal pop performance at power up
#----------- Rpop used is 6k with N = 6 & soft step = 20usec.
w 30 14 29
#----------- Power up HPL and HPR drivers
w 30 09 30
#----------- Wait for 2.5 sec for soft stepping to take effect
#----------- Else read Page 1, Register 63d, D(7:6). When = “11” soft-stepping is complete
#----------- Select page 0
w 30 00 00
#----------- Power up left DAC
w 30 3f 94
#-----------
#----------- Power up the left and right DAC channels and route the left channel I2S data
#----------- to left channel DAC and right channel I2S data to right channel DAC
w 30 3f d4
#----------- Unmute the DAC digital volume control
w 30 40 00
#----------- Change Beep length
w 30 4a 10
#----------- Generate a Beep
w 30 47 80

Thanks again for your reply,
Cyril

Hi, Cyril,

Excuse me, could you provide your clock settings too, please? I suspect that the issue is related with this.

Best regards,
Luis Fernando Rodríguez S.

The only clock received by the tlv320 is the mclk clocked at 25MHz.

Hi, Cyril,

Could you try disabling the weak AVDD to DVDD connection with Page 1 / Register 1? Also, could you try configuring the PowerTune Mode in PTM_P4 to get the best performance? (Page 1 / Register 3-4).

Regarding your audio file, are you using a .wav file?

Best regards,
Luis Fernando Rodríguez S.