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TLV320AIC3104 Master Mode extra clock pulse

Michael Burns
Intellectual 440 points
Other Parts Discussed in Thread: TLV320AIC3104, MSP430F5340

I am using a TLV320AIC3104 Codec in Master Mode. The sample rate is 16 kHz and the data width 16 bits, so the length of the WCLK pulse should be 31.25 usec and there should be 16 clock pulse during the time WCLK is high and another while WCLK is low. After enabling the ADC, the first WCLK pulse is high for 33.2 usec during which time 17 clock pulses are generated. Subsequent  cycles are as expected (WCLK pulse width is 31,25 usec during which 16 clock pulses are generated). The Codec is connected to the SPI bus of a MSP430F5340 (operating in Slave Mode). The extra clock pulse is causing the data received by the MSP to be shifted by one bit.

I have the Codec set to left-justified mode.

Is this normal for a TLV320AIC3104? Any way around it?

Mike

  • 0
    TI__Guru* 84915 points
    Hi, Mike,

    Could you provide your registers configuration and the MCLK frequency that you're using? This is to have a better approach to this issue.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 440 points

    Hello Luis.

    The register settings are as follows:

    void init_TLV320AIC3104(void)   // Initialize the TLV320AIC3104 CODEC registers
    {

    // TLV320AIC3104 Setup

    // Reset the Codec

      writeCodecRegister(SOFTWARE_RESET, CODEC_RESET);
     
    // Set fsref to 48 kHz (MCLK is 12.288 MHz)
     
      writeCodecRegister(PLL_PROGRAMMING_REG_A, 0x10);            // Disable PLL; Set Q = 2
      writeCodecRegister(CODEC_SAMPLE_RATE, 0x44);                // ADC and DAC Sample Rate = fsref/3 (16 kHz)
       
    // Set up the Serial Data Interface 
     
      writeCodecRegister(SDI_REG_A, 0xC0);                        // BCLK and WCL are Outputs (Master Mode)
      writeCodecRegister(SDI_REG_B, 0xC0);                        // Serial Data Bus uses left_justified mode; Audio data word length = 16 bits

    // ADCs
    //
    // Only the Left ADC is used, using the MIC1L inputs
     
    //  writeCodecRegister(LEFT_ADC_PGA_GAIN, 0x50);                // Enable Left ADC PGA and set gain to 40 dB
      writeCodecRegister(LEFT_ADC_PGA_GAIN, 0x00);                // Enable Left ADC PGA and set Gain to 0 dB
      writeCodecRegister(MIC1LP_LEFTADC, 0x84);                   // MIC1LP/MIC1?M are cofigured in differential mode; Power Up Left ADC
       
    // DACs
    //
    // In this application, the DACs are not used
     
      writeCodecRegister(DAC_PWR_DRIVER_CNTRL, 0x00);             // Leavs both DACs unpowered
     
      return;
    }

    As shown above, MCLK frequency is 12.288 MHz.

    Mike

  • 0 in reply to Michael Burns
    TI__Guru* 84915 points
    Hi, Mike,

    I reviewed your register configuration. Could you try configuring the Page 0 / Registers 8 & 9 for Place DOUT in high-impedance state when valid data is not being sent (P0 / R8 / B5) and Re-sync stereo ADC/DAC with codec interface if the group delay changes by more than +/- fs/4 (P0 / R9 / B1-2)?

    Best regards,
    Luis Fernando Rodríguez S.