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C6727 McASP and Multiple AIC33

Dhar Kurban
Intellectual 960 points

I have a C6727 connected to 3 AIC33 on the same McASP.

The DSP is the master (source of clock and frame).

I am trying to configure each AIC33 at a different sample rate.

In the data sheet for the AIC33 it mentions different sample rates for ADC and DAC and having the WCLK as the higher of the 2 rates. If that is possible then I am guessing there is some way of having an AIC33 configured with a lower sample rate than the WCLK.

How does the DSP know when/where to place the data if the frame sync is higher than the sample rate?

How does the AIC33 know when to latch the data if the frame sync doesn't match the sample rate?

The Paragraph in the AIC33 data sheet is as follows:

"The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC
and DAC sampling frequencies."

 

Thanks

Dhar

  • 0
    TI__Mastermind 46195 points

    Dhar,

    You program the PLL and/or divider settings (i.e. NADC/NDAC) for different sample rates. If the codec is the slave, the internal conversion is a function of these settings and data handoff of this conversion will be done at the rate imposed by WCLK. Under normal circumstances, WCLK and the internal converters are set for the same sample rate.

    If we go to an extreme on the ADC (e.g. internal sample rate is double than WCLK), then you will have repeated samples. If it is half, you will receive half the samples (which can cause aliasing if not pre-filtered). We provide a secondary pin for WCLK that can run at a different rate than WCLK for cases where ADC and DAC sample rates differ. Since BCLK is shared between both, its minimum frequency must be 32*FS, where FS is the fastest sample rate.

    Regards,

    J-