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AIC3263 | Differential Class D speaker output

divhkk
Intellectual 310 points

Hi. We are trying to configure our codec for differential output from Class-D speaker amplifier. This is the register configuration we have used:

  1. Lineout Amplifier Control: B0_P1_R22 = 0x87
  2. Speaker Amplifier Control 1: B0_P1_R45 = 0x06
  3. Speaker Amplifier Control 2: B0_P1_R46 = 0x00
  4. Speaker Amplifier Control 3: B0_P1_R47 = 0x80
  5. Speaker Amplifier Volume Controls: B0_P1_R48 = 0x21 (SPK Driver volume = 0x12dB, SPK_RIGHT_CH_IN not muted)
The above configuration is according the config described in “Figure 2-8. Single Channel Input to Differential Line-out”  of document SLAU475 (AIC3263 Reference Guide).
  1. LDACM has been routed to LOL
  2. LOL output has been routed to LOR
  3. LOL and LOR have been routed to SPK and SPK_RIGHT_CH_IN respectively.

But we find that the output from SPK-M and SPK-P pins are in phase. 

Please let know what changes we need to make in order to obtain differential output.

  • 0
    TI__Guru* 84915 points

    Hi,

    The configuration seems to be all in order. However, you should ensure that the signal is not muted. When both SPK outputs are in phase, there could be a register in mute mode. Ensure that DAC, volume blocks and speaker registers are all enabled and un-muted. Additionally, I suggest to take a look at 2.3.12 Example Setup for Class-D Routing section of application note.

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 310 points
    Thank you for the response.

    So, if the SPK_RIGHT_CH_IN is muted, the speaker output might be in phase?
  • 0 in reply to divhkk
    TI__Guru* 84915 points
    Exactly.

    You should be able to see differences in phase when all the DAC, volume and speaker blocks are un-muted. Also, the data serial interface should be configured properly to get the signal as expected.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 310 points

    I see.  

    Our playback seems to work. It is just that the speaker output is not differential. Also, we have a mono signal (data only on the left channel).

    Q1. Would that change anything?

    Here are all the register settings related to speaker output:

    1. B0_P0_R63 = 0xC0
    2. B0_P0_R64 = 0x00
    3. B0_P0_R65 = 0x00
    4. B0_P0_R66 = 0x00
    5. Lineout Amplifier Control: B0_P1_R22 = 0x87
    6. Speaker Amplifier Control 1: B0_P1_R45 = 0x06
    7. Speaker Amplifier Control 2: B0_P1_R46 = 0x00
    8. Speaker Amplifier Control 3: B0_P1_R47 = 0x80
    9. Speaker Amplifier Volume Controls: B0_P1_R48 = 0x21 (SPK Driver volume = 0x12dB, SPK_RIGHT_CH_IN not muted)

    Q2. Is there any other register that needs to be configured?

    Q3. Do registers B0_P0_R63/B0_P0_R64 have to be initialized after Lineout and speaker amplifier control registers (B0_p1_R22 - R48)? Is there a recommended order to initialize them? Would the order affect the speaker output?

    Thank you.

  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 310 points
    1. We configured the EVK for the above register settings and we probed LLOUT and RLOUT, as well as SPK-M and SPK-P. The Lineout pins have a differential output, but the speaker output is not differential. Is there any reason why LOL and LOR are differential but SPK-P and SPK-M are not?
    2. We read back register B0_P0_R38 to be 0xBB. This indicates that primary left and right DAC PGA are not muted, but secondary left and right DAC PGA are muted. Do you think this may be the cause for spk output not being differential? If it is, how to unmute the secondary DAC PGA?

    Thank you.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 10 points
    Hello Luis,

    We tested your EVM with class D speaker and saw the same thing: both signals are in phase. The speaker is working. The reasons we are asking how to get the differential output are CMRR and output filtering configuration.

    Could you please test TI EVM and see it?

    Best Regards,
    ~Natallia Holubeva
  • 0 in reply to Natallia Holubeva86
    TI__Guru* 84915 points

    Hello, Natalia,

    I tested the Class-D speaker configuration in the TI EVM. The Class-D speaker lines will be in phase until you send audio data via I2S. If the I2S lines don't receive anything, the speaker lines will be in phase even if they are un-muted. Please see the attached script for reference and let me know if you have more questions or comments.

    Fullscreen Class_D_script.txt Download 
    #######################################################
# Class-D Speaker Playback
# -----------------------------------------------------
# Description:
# - 44.1kHz/48kHz Sampling Rate.
# - USB Audio Playback.
# - LOL and LOR are mixed -6dB/-6dB to convert stereo
#   to mono in analog.
#
# Hardware Setup:
# - Default.
#
# Revision History:
# - Version 1.1, 2013-07-23
#   - Added FIFO Configuration section.
# - Version 1.0, 2013-06-21
#   - Initial Release.
#
# Devices:
# - TLV320AIC3263
#######################################################

#######################################################
# Software Reset
#######################################################
w 30 00 00 # Initialize to Page 0
w 30 7f 00 # Initialize to Book 0
w 30 01 01 # Software Reset
d 1        # Delay 1 millisecond

#######################################################
# FIFO Configuration
#######################################################
w 30 00 00 # Select Page 0
w 30 7f 78 # Select Book 120
w 30 32 80 # Enable DAC FIFO
w 30 7f 64 # Select Book 100
w 30 32 80 # Enable ADC FIFO
w 30 7f 00 # Select Book 0

#######################################################
# Power and Analog Configuration
#######################################################
w 30 00 01 # Select Page 1
w 30 01 00 # Disable weak AVDD to DVDD connection
w 30 7a 01 # REF charging time = 40ms

#######################################################
# Clock configuration
# -----------------------------------------------------
# - MCLK = 11.2896MHz/12.288MHz
# - FS = 44.1kHz/48kHz
# - I2S Slave
#######################################################
w 30 00 00 # Select Page 0
w 30 04 00 # Set DAC_CLKIN as MCLK
w 30 0b 81 # NDAC = 1
w 30 0c 82 # MDAC = 2
w 30 0d 00 # DOSR = 128
w 30 0e 80 # DOSR

#######################################################
# Audio Serial Interface #1 Configuration
#######################################################
w 30 00 04 # Select Page 4
w 30 01 00 # ASI1 set to I2S mode, 16-bit
w 30 0a 00 # ASI1 WCLK/BCLK to WCLK1 pin/BCLK1 pin

#######################################################
# Signal Processing Settings
#######################################################
w 30 00 00 # Select Page 0
w 30 3c 01 # Set the DAC PRB Mode to PRB_P1

#######################################################
# Output Channel Configuration
#######################################################
w 30 00 01 # Select Page 1
w 30 03 00 # Set PTM mode for Left DAC to PTM_P3
w 30 04 00 # Set PTM mode for Right DAC to PTM_P3
w 30 16 c3 # DAC to LOL/R routing, power-up LOL/R
w 30 2E 0c # Route LOL to SPK @ -6dB
w 30 2F 0c # Route LOR to SPK_RIGHT_CH_IN @ -6dB
w 30 30 21 # SPK Gain = 12dB, unmute SPK_RIGHT_CH_IN
w 30 2D 06 # Power-up SPK, route SPK_RIGHT_CH_IN to SPK
w 30 00 00 # Select Page 0
w 30 3f c0 # Power up the Left and Right DAC Channels
w 30 40 00 # Unmute the DAC digital volume control

    Best regards,
    Luis Fernando Rodríguez S.