TLV320DAC3120 Configuration Settings

Hi, Thulasiram,

Welcome to E2E and thank you for your interest in our products!

342KHz is actually the Class-D frequency in this DAC. This means that you are configuring correctly the Class-D driver. However, there should be something muted in your configuration. I noticed that Page 1 / Register 38 is configured as 0xff. Table 5-19 shows the selected value for the speaker amplifier. In this case, the selected value is 127 (0x7f for bits D6-D0). So, I recommend to modify this register with the correct volume gain.

Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,


I modified the register page1/Register 38 with 0x87 and checked, Still Iam getting the same problem.

Thanks,
Thulasiram C

Hi Luis,

In the settings I have typed Reg 5 -> 0x13 wrongly but I configured as Reg 5 -> 0x93H only.

Thanks,
Thulasiram C

Hi, Thulasiram,

I would recommend to configure Page 1 / Register 32/ Bit D0 as 0. It seems that this bit is being configured as '1'. This is a read-only bit that detects short-circuit in the speaker lines. So, this could be affecting the behavior. Also, have you verified if the headphone output generates the signal correctly? Could you try this, please?

I also suggest to take a look at our example configuration of the TLV320DAC3120. The code lines format is w (write) 30 (I2C address) xx (register address in hex format) yy (register value in hex format).

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 11.2896 MHz,
# BLCK = 2.8224 MHz, WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL_clkin = MCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=8, D=0000
w 30 04 03 91 08 00 00
#
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 128
w 30 0D 00 80
#
# NADC = 2, MADC = 8, dividers powered on
w 30 12 82 88
#
# AOSR = 128
w 30 14 80
#
###############################################

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P5, PRB_R5
w 30 3c 05 05
#
# Enable Adaptive Filtering
w 30 00 08
w 30 01 04
#
###############################################

##########################################
# Configure Class-D Output
##########################################
#
# Switch to Page 1
w 30 00 01
#
# CM = 1.65V
w 30 1f 14
#
# Unmute Class-D (6dB)
w 30 2a 04
# Unmute Class-D (12dB)
# w 30 2a 0c
# Unmute Class-D (18dB)
# w 30 2a 14
# Unmute Class-D (24dB)
# w 30 2a 1c
#
# Power-up Class-D driver
w 30 20 86
#
# Route Analog Volume Control to Class-D Driver, 0dB
w 30 26 80
#
##########################################

##########################################
# Configure HP Output
##########################################
#
# Switch to Page 1
w 30 00 01
#
# De-pop, Power on = 800 ms, Step time = 4 ms
w 30 21 4e
#
# Route Analog Volume Control to HP Driver, 0dB
w 30 24 80
#
# HP output powered up, current limit
w 30 1f 84
#
# HP unmute and gain 0db
w 30 28 06
#
##########################################

##########################################
# Configure DAC Channel
##########################################
#
# Switch to Page 1
w 30 00 01
#
# DAC routed to Mixer Amplifier
w 30 23 40
#
# Switch to Page 0
w 30 00 00
#
# Powerup DAC, DAC => LI2S, soft-step disable
w 30 3f 96
#
# Unmute DAC, 0dB
w 30 40 04 00
#
##########################################


Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,


I configured Page 1 / Register 32/ Bit D0 as 0 and checked that , it is not working. Apart from that the configuration you have provided mostly I followed and checked but it is not working.

Here in my case there is no MCLK given to the DAC. I configured the DAC with the following settings for clock generation

Reg 4 -> 0x07; //PLL_CLKIN = BCLK && CODEC_CLKIN = PLL_CLK
Reg 5 -> 0x93; //PLL ON && P = 1, R = 3
Reg 6 -> 0x14; // J = 20
Reg 7 -> 0x00; // D Val MSB
Reg 8 -> 0x01; // D val LSB
Reg 11 -> 0x80 | 0x05; // NDAC POWER ON | NDAC_VAL
Reg 12 -> 0x80 | 0x03; // MDAC POWER ON | MDAC_VAL
Reg 13 -> 0x00; //DOSR MSB(9:8)
Reg 14 -> 0x80; //DOSR LSB(7:0)

Reg25->0x03; // Selected CDIV_CLKIN = PLL_CLK
Reg 26 0x81; // CLKOUT M divider is powered up. and divider value is 1.

But Iam not seeing any clk in the GPIO1 (CLKOUT) . Could you provide your inputs on this.

How can I conform whether the PLL_CLK is generated or not??




Thanks,
Thulasiram C

Hi, Thulasiram,

You should configure Page 0 / Register 51 (GPIO1 In/Out Pin Control) in order to use GPIO1 as CLKOUT. Once you power on the DAC, you should be able to see the clock pulses on this pin.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

I configured page 0/Register 51 (GPIO1 In/Out Pin Control) as CLKOUT, and I selected the PLL_CLK as CLKOUT by configuring the register Page 0 / Registers 25: CLKOUT MUX. But Iam Seeing a random signal as the output that too irrespective of PLL_CLK_IN which is in my case BCLK.

When I tried to select BCLK as CLKOUT. Iam able to see the exact clock on the GPIO1 pin.

Looks like the PLL is not generating any clock. Here the PLL _CLK_IN = BCLK which will come only when the I2S data goes as it is protocol bit clock.

Is it manadatory to provide a continuos clock ( MCLK ) as the PLL_CLK_IN ??

The PLL is powered on indication is that Iam getting a random signal on the GPIO1 when I configured PLL_CLK as CLKOUT.


Thanks,
Thulasiram C

Hi, Thulasiram,

Have you tested CLKOUT as DAC_CLK and DAC_MOD_CLK? Did you get a random signal too?

Then, the PLL needs of 10ms to be completely initialized. Did you add this delay after the initialization?

The PLL_CLK_IN needs a continous clock. It can be taken from MCLK, BCLK, GPIO1 or DIN as shown in Figure 5-17 of datashet.

Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

Hello !

I also try to get a "beep" from the TLV320DAC3120.
I have a 11,895910 MHz clock at MCLK, currently using the PLL.

(I also tried without PLL using a 33MHZ MCK and other Divider settings, same result! )


I used this script supplied from someone from TI here at the forum:


###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 11.2896 MHz,
# BLCK = 2822.4 KHz, WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL ON
w 30 04 03 91 08 00 00
#
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 128
w 30 0D 00 80
#
###############################################

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_R25 for beep generation
w 30 3c 19
#
###############################################

##########################################
# Configure HP Output
##########################################
#
# Switch to Page 1
w 30 00 01
#
# De-pop, Power on = 1.22s, Step time = 3.9 ms
w 30 21 4e
#
# HPL and HPR powerup, current limit, CM = 1.35V
w 30 1f D4
#
# HPL and HPR unmute and gain 0db
w 30 28 06 06
#
##########################################

##########################################
# Configure DAC Channel routing to HP
##########################################
#
# Switch to Page 1
w 30 00 01
#
# DACs routed to HP
w 30 23 44
#
# Mixer to HPL/R
w 30 24 80 80
#
# Switch to Page 0
w 30 00 00
#
# Powerup DACs
w 30 3f D4
#
# Unmute DACs, 0dB
w 30 40 00 00 00
#
##########################################

##########################################
# Configure DAC Channel routing to SPK
##########################################
#
# Switch to Page 1
w 30 00 01
#
# Unmute Class-D (6dB)
w 30 2a 04
#
# Power-up Class-D driver
w 30 20 86
#
# Mixer to Class-D Driver, 0dB
w 30 26 80
#
##########################################
#
# switch to page 0
w 30 00 00
#
# Beep lengh of 1000 cycles
w 30 49 00 AC C4
#
# Coeff for 1KHz, 44.1KHz sampling
w 30 4C 12 2D 7E B4
#
# Start beep
w 30 47 80 80
############################################

This (below) are the values I read BACK from the chip after sending the scripts data.
I set a very long beep time I used , but I cannot hear anything.
On the scope I only see the 320kHz PWM at the loedspeaker output, which means that it is turned on.

The READ Back values of REG 1 is OK, its self resetting
The beep start at the end is not set back, may be due to the long set beep time.


PAGE 0 REG 1 VALUE 0,
PAGE 0 REG 4 VALUE 3,
PAGE 0 REG 5 VALUE 91,
PAGE 0 REG 6 VALUE 8,
PAGE 0 REG 7 VALUE 0, 0,
PAGE 0 REG 11 VALUE 82, 88,
PAGE 0 REG 13 VALUE 0, 80,
PAGE 0 REG 60 VALUE 19,
PAGE 1 REG 33 VALUE 4e,
PAGE 1 REG 31 VALUE d4,
PAGE 1 REG 40 VALUE 6, 6,
PAGE 1 REG 35 VALUE 44,
PAGE 1 REG 36 VALUE 80, 80,
PAGE 0 REG 63 VALUE d4,
PAGE 0 REG 64 VALUE 0, 0, 0,
PAGE 1 REG 42 VALUE 5,
PAGE 1 REG 32 VALUE 86,
PAGE 1 REG 38 VALUE 80,
PAGE 0 REG 73 VALUE ff, ac, c4,
PAGE 0 REG 76 VALUE 12, 2d, 7e, b4,
PAGE 0 REG 71 VALUE 80, 80,

My Question is : Is a Clock at BCLK or WCLK required to get the BEEP ?
Or is the MCLK and a proper divider setting enough ??

Hi, Wolfgang,

Welcome to E2E and thank you for your interest in our products!

The TLV320DAC3120 requires a BCLK and WCLK to generate a beep. This register configuration configures the device in slave mode, which means that the DAC requires external BCLK and WCLK. If you cannot generate external clocks, I would recommend to place the device in master mode. This mode is used to generate the BCLK and WCLK from the DAC3120. You would need to configure page 0 / register 27 to place both clocks in output mode. Then, enable the BDIV_CLKIN to get an output from BCLK (page 0 / register 30).

For additional information about the beep generation, please take a look at the document below:

www.ti.com/.../slaa446.pdf

I hope this helps!

Best regards,
Luis Fernando Rodríguez S.

Hey Luis Fernando!

Meanwhile I did what I mentioned in my posting, and generated the BCLK and WCLK, and as you wrote, the beep works.
I use the DAC as slave with a PIC32MZ as master, and also my first configuration without using the DAC
internal PLL runs now also :-)
I saw no where in the datasheet that BCLK and WCLK are needed for the internal beep, I thought
that the MCLK clock is enough :-) Ok, now I know I was wrong.


One more question using the I2S Interface: Do I get sound over the DAC without processing the data by the
mini DSP ? ( ok filtering is missing then) or is it needed to set up the DSP in any case ?

With best regards
Wolli

Hi, Wolli,

There's no need to configure the miniDSP or processing blocks to get sound over the DAC. Basically, the processing blocks and miniDSP are used for filtering purposes. If you don't need to add a filter in your design, you may set the miniDSP and processing blocks in default state.

Best regards,
Luis Fernando Rodríguez S.