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SRC4392 EMC Issues

Orangefordj
Prodigy 10 points
Other Parts Discussed in Thread: SRC4392

Hi All

I have a new design which uses the SRC4392. The circuit works great and the SRC does its job of upsampling to 24/192 perfectly. Unfortunately as soon as we turn on the SPDIF output attached to TX+ pin 32 the PCB and any attached cables radiate at 10 - 15dBuV above the limit at various multiples of the 24.59 MHz clock. Knitting the digital and analog internal ground planes together has helped and so has reducing the overall output level of the SPDIF but there are still four or five spikes up to 5dB over the limit. Filtering the SPDIF output seems to render it useless long before the EMC issue is solved.


Has anyone else experienced this issue? If so any tips on how you overcame it would be greatly appreciated.

  • 0
    TI__Mastermind 28020 points
    Hi,

    The PLL in the part will output a system clock at 98.304 MHz and that will be divided down to be used for each port. There is not much that can be done about this clock within the part. So external options are the only choice. Do you have a series resistor on the trace already? this may help with reflections. What filters have you tried so far, and RC or a ferrite bead? Which EMC standard are you trying to pass?

    Justin