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TLV320aic3106 SPI write delay

gilbert vellet
Prodigy 175 points
Other Parts Discussed in Thread: TLV320AIC3106, OMAPL138

1- In the TLV320AIC3106 datasheet page 43, the section 11.5.1.1.2 says that between 2 SPI write accesses, the chip select should be negated for a minimum of 6.25us. This limitation applies to the registers related to the audio output drivers mux, mix, gain configuration, etc. Do you have a more precise list of which registers need this delay?

2- Is there a way to reduce this delay, for instance by using a slower SPICLK?


I ask this question because this delay is too big to be taken in charge by the omapl138 SPI engine. I have to make a software delay between each access.


Thanks

  • 0
    TI__Guru 57800 points

    Hi, Gilbert,

    The engineer supporting this device has been notified and will help you with your questions. He will get back to you early next week. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    TI__Guru* 84915 points
    Hi, Gilbert,

    1. Basically, the registers that the datasheet refers to are Page 0 / Registers 45 - 93. All these registers control the audio analog output mixers, muxers, gains...

    2. There's no way to reduce this delay. This time should be respected in order to configure correctly these registers. If this delay is not considered, there could be a risk to have a wrong configuration of these registers (such gains, signal paths, etc.).

    Best regards,
    Luis Fernando Rodríguez S.