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TAS6424 / Layout Guide-line

Kuramochi Tadahiko
Guru 28715 points

Hi,

The datasheet P56 says that "The traces from the output pins to the inductors, D, should have the shortest trace possible to allow for the smallest loop of large switching currents.".

I think that the traces" D" doesn't consist of loop of large switching currents, because the loop is consisted of H-side SW, L-side SW, input capacitor.

Is my understanding wrong? 

(I'm agree with placing inductor close to output pin to decrease switching node area)

And the EVM seems to connect inductors placing solder-side through vias.

Is it allowed?

Best Regards,

Kuramochi

  • 0
    TI__Mastermind 33420 points

    Hi Kuramochi-san,

    Yes, you are correct that the output + the inductor + capacitor + the ground pin of the device should be layout as short loop as possible for the switching current ripple.  This current ripple can be large but the mojority of the current is the power going through the load (audio).

    Some of the outputs connect to the inductors through vias to the bottom side on the EVM.  This is okay as long as the loop (output + inductor + cap + ground pin) is short.

    Hope this helps.

    Regards,

    Tuan

  • 0 in reply to Tuan
    Guru 28715 points

    Luu-san,

    Thank you for your answer.
    I understood.

    Can it be allowed to replace ±inductors on the each bord side such as following if the loop is short?

    Parts side ：1ch+,2ch+,3ch+,4ch+
    Solder ：1ch-,2ch-,3ch-,4ch-

    Best Regards,
    Kuramochi

  • 0 in reply to Kuramochi Tadahiko
    TI__Mastermind 33420 points

    Hi Kuramochi-san,

    I have seen the placement done with 1ch+ on one side and 1ch- on the other side (and the same with the other 3 channels).  As long as the (+) channels and (-) channels (including the trace routings) are on top of each other, it should be okay.  As you mentioned, it is for keeping the current loop short and for minimizing the common mode noise.

    Have a good weekend.

    Regards,

    Tuan