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PCM1795 :Timing requirement specification

yoshiki hasebe
Mastermind 6385 points
Other Parts Discussed in Thread: PCM1795

Dear Sirs,

My customer asked us about  timing requirement specification.

When they confirmed with actual board equipped with PCM 1795, they were out of specifications with the following items.

1.Data hold time(t(D-HD)
  Spec（Max)：900ns　⇒　996ns
2.Fall time of SCL / SDA signal（t(SCL-F) (t(SDA-F)
  Spec(min):20 + 0.1 CB ns  ⇒  8 ns
So please tell me the following questions.
　
1) When Data hold time becomes larger than prescribed max value What kind of problem is concrete?
2) When the SCL / SDA Fall time becomes smaller than the prescribed min value What kind of defects can be considered concretely?
3) Please tell me why Fast mode and Standard mode are set to the same.
Best Regards,
Y,Hasebe
    
  • 0
    TI__Expert 5645 points

    Dear Hasebe-san,

    As you already know, Hold time is defined as the time interval after sampling has been initiated. This interval is typically between the falling SCL edge and SDA changing state. Even when operating in Fast-Mode, we are operating at 400kHz clock (2.5uS period). As we sample at subsequent rising edge, if the hold time exceeds by 90nS, there should not be any anticipated problem.

    There should be no issue with the fast(er) rise time either.

    As far as Fast/Standard modes go, it's usually the setup time that is much lower in Fast-mode compared to Standard mode. The I2C spec does not mention the max value for data hold-time for Standard mode, but PCM1795 does have a max value of 900ns.

    Hope this answers your questions. Thanks.

    Best regards,

    Ravi

  • 0 in reply to Ravi Patil
    Mastermind 6385 points

    Hello Ravi-san,

    Thank you for your reply.

    I sent  your comments to my customer.

    Then they asked us additional question.

    On my customer's board, they are using around SCL = 88 kHz
    It operates at a slightly slower frequency than the max specification in Standard mode.
    In this case, the speed of SDA also lags accordingly, so we think that time will be longer as Hold Time.
     
    When SCL is 100 kHz, they think whether it can be achieved within 900 ns.

    However, if the frequency of SCL slows down, they think that hold time will be longer.

    If it is lower than 100 kHz like this actual machine, is it not necessary to change the specified value within 900 ns according to the speed of SCL operating frequency?
    (Eg 900 ns × 100 kHz / 88 kHz)

    Best  Regards,

    Y.Hasebe

  • 0 in reply to yoshiki hasebe
    Mastermind 6385 points
    Hello Ravi-san,

    I am being requested again to answer the question from my customer.
    Please let me know about the above additional questions.

    Best Regards,
    Y.Hasebe
  • 0 in reply to yoshiki hasebe
    Mastermind 6385 points

    Hello　Ravi-san,

    Please give me some comments about my additional question.

    Best Regards,

    Y.Hasebe

  • 0 in reply to yoshiki hasebe
    TI__Expert 5645 points
    Hi Hasebe-san,
    As far as the datasheet parameters go, they are specified based on detailed pre-silicon verification and post-silicon validation. In this case, the data hold time (max) is specified for standard mode and fast mode based on the evaluating the part w. nominal clock speed of 100kHz for standard mode and is guaranteed to work as expected.

    However, it's quite possible that when the host clock is lower (in this case, 88kHz for customer design), it's quite possible that the PCM1795 should perform reliably w. data hold time >900nS although it's greater than the max value. The datasheet parameter will still reflect 900nS max assuming the clock speed of 100kHz nominal for most application.

    Hope this clarifies things w. data hold-time. Thanks.

    Best regards,
    Ravi