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Some question about GAIN SETTING of PGA2310

Ying-Zhi Zhou
Prodigy 10 points
Other Parts Discussed in Thread: PGA2310

The datasheet of PGA2310 in P.9 is describe serial interface timing requirement.My question is how PGA2310 check the signal of SDI.

Is CS in LOW and SCLK in LOW to HIGH??

The duty cycle of SCLK isn't 50%. Can it works??

Thanks

  • 0
    TI__Guru* 97755 points

    To communicate with the PGA2310, the CSn must first be set low. The data bytes are latched when SCLK goes from low to high. I also believe that the data word is latched when the CSn is raised from low to high. Most of this is described in Figure 2 of the PGA2310 datasheet on page 8.

    It is ok if the duty cycle isn't 50%. However, there aren't too many listed guidelines on the requirements. In the specification table on page 3, the SCLK frequency maximum is 6.25Mhz, while the minimum SCLK width high or low is 80ns. I would guess that if all of these requirements are met, then the data should be fine.

     

    Joseph Wu