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TLV320AIC3268: TLV320AIC3268 - Crackling on LOL/LOR When Switching Between I2S Sources

Phil Hale
Intellectual 630 points
Part Number: TLV320AIC3268


I have a switch changing I2S sources being sent to the TLV320AIC3268. In some cases, there is a crackling/static kind of sound for the first 1/2 to 1 second coming from the LOL/LOR section. We are routing the LOL/LOR to an external amplifier to better hear the artifact. It's clear on the LOL/LOR but not apparent on the I2S output of the TLV320AIC3268.

I have tried to shut down the DAC during the switch and turn it back on after the switch to give the AS1 time to adjust to the new I2S signal but that didn't help. Of course, I tried turning the LOL/LOR master volume down to nothing during the switch but that also didn't help.

Any idea how we can reduce this artifact?

Thank you!

Phil

  • 0
    TI__Guru* 84915 points
    Hi, Phil,

    Could you provide your register configuration to verify if this could be a root cause? Additionally, have you verified if the I2S lines respect the recommendations of datasheet (times, capacitance, etc.)?

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 630 points
    Luis,

    We are trying to get you that information.

    In the meantime, I should add that we are using the BCLK as the primary inbound clock so the TLV320 adjusts automatically when the audio sample frequency changes at the source. The I2S audio is being extracted from an HDMI video signal and the audio sample frequency changes from 32, 44.1, 48, 96, or 192kHz based upon the source being used and we are switching between multiple HDMI sources.

    Sometimes there is almost no crackling when switching between sources. I suspect the lack of crackling is because the audio sample frequency rates are the same. E.g. we are going from one source at 44.1kHz to another source at 44.1kHz.

    Once the crackling stops, the audio sounds fine regardless of the audio sample rates.

    Finest regards,

    Phil
  • 0 in reply to Phil Hale
    TI__Guru* 84915 points
    Hi, Phil,

    Could you try using a fixed clock source to generate the codec sampling rate? We don't recommend to change the clock source or modify the sampling rate while the ADC/DAC blocks are powered up. Is it possible in your application?

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 630 points
    Luis,

    Thank you for you quick response.

    We can use the MCLK as the input clock and set the PLL to match that audio sample frequency. I believe we have done this before and it works for us. The problem is adjusting the PLL's P, R, J, and D constants on the fly to match the audio sample frequency.

    Is there a way to detect the audio sample frequency and have the P, R, J, and D registers automatically change or at least allow us to sample the inbound audio, detect the audio sample frequency and adjust the P, R, J, and D registers accordingly?

    Regards,

    Phil
  • 0 in reply to Phil Hale
    TI__Guru* 84915 points
    Hi, Phil,

    Yes, please try using the MCLK as input clock and modify the PLL values. Normally, we don't recommend to modify the PLL values with the ADC and DAC running, but since there's no way to automatically change the P, R, J and D values or detect the sample frequency, the only way to do this would be modifying the PLL values on the fly.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 630 points
    Luis,

    The problem has been resolved. Probably not the preferred method.

    The crackling occurs no matter what one does with the P, R, J, and D values. Nor does the crackling stop if using the MCLK or BCLK. When switching the I2S, the DSP needs some time to adjust to the new data stream.

    I resolved the problem by disabling the LOL/LOR routing:
    0x30 0x00 0x01 // Page 1
    0x30 0x16 0x03 // Disconnect LOL/LOR but leave LOL/LOR powered up.
    (connect the new I2S signal)
    (delay 1.0 second)
    0x30 0x00 0x01 // Page 1
    0x30 0x16 0xC3 // Connect LOL/LOR to DAC

    The delay provides time for the DAC to adjust to the new I2S signal prior to routing the signal to the LOL/LOR output. From what I can tell, the delay is not needed if the audio sample rate is the same between the two sources. However, if one was listening to an 44.1 kHz source and switches to a new I2S signal that was sampled at a rate of 48 kHz a crackle will occur for the first 1 to 1.5 second until the DSP adjusts. At least this was my experience in this case.

    Thank you for your assistance and getting me pointed in the right direction!

    Phil