HI,Tier.
I have some problems with configure PCM1865 on my own test PCB.
I need it to be working with ADAU1451, in slave mode, TDM data output, 4 ch. 48kHz, clock on SCK and BCK is 12.288MHz, LRCK - 48kHz.
So, first, I don`t understand which section for configurate I should use. Table 10 or table 13 in documentation (I try all of them). I also use Enable Auto Clock Detector Configuration.
This is my last config table (there may be some mistakes in comments).
uint8_t ADC_InitTable[ADC_INIT_TABLE_LEN][2] = {
// {Адрес регистра, значение}
//{ADC_PAGE_SEL_REG, ADC_PAGE_RESET}, //Page RESET
//Page 0
{ADC_PAGE_SEL_REG, ADC_PAGE_SEL_0},
{0x05, 0x00}, // Disable Clipping Detection After Digital PGA, PGA Control - Immediate Change
{ADC_REG0_ChanSel_1L, 0x10}, // ADC Input Channel Select ADC1L - {VIN1P, VIN1M}[DIFF]
{ADC_REG0_ChanSel_1R, 0x01}, // ADC Input Channel Select ADC1R - VINR1[SE]
{ADC_REG0_ChanSel_2L, 0x00}, // ADC Input Channel Select ADC2L - No Select
{ADC_REG0_ChanSel_2R, 0x20}, // ADC Input Channel Select ADC2R - {VIN3P, VIN3M}[DIFF]
{0x0B, 0x57}, // Receive PCM Word length - 24bit; TDM_LRCK_MODE - duty cycle of LRCK is 1/256; Stereo PCM Word length - 24bit; Serial Audio Interface Format - TDM/DSP (256Fs BCK is required)
{0x0C, 0x01}, // Select TDM transmission data. 01: 4ch TDM - DOUT1: ch1[L], ch1[R], ch2[L], ch2[R]
{0x0D, 0x00}, // TX_TDM_OFFSET[7:0] - 0 BCK
{0x0E, 0x00}, // RX_TDM_OFFSET[7:0] - 0 BCK
{0x15, 0x01}, // Disable the pull down of GPIO0 (pin 22)
{0x20, 0x42}, // (0x4E) SCK/Xtal selection; Master-Mode SCK source select; Master/Slave selection; ADC Clock Source selection; DSP2 Clock Source selection; DSP1 Clock Source selection; Enable Auto Clock Detector Configuration
{0x21, 0x03}, // 0x03 DSP1 Clock Divider Value 3: 1/4
{0x22, 0x00}, // 0x07 DSP2 Clock Divider Value 7: 1/8
{0x23, 0x01}, // 0x0F ADC Clock Divider Value 15: 1/16
{0x28, 0x01}, // Enable the PLL, PLL Reference clock selection - SCK
{0x29, 0x01}, // 0x03 PLL P-Divider value
{0x2A, 0x01}, // PLL R-Divider value
{0x2B, 0x08}, // 0x10Integer part of the PLL J.D-Divider value
{0x2C, 0x00}, // Fractional part of the PLL J.D-Divider value. (Least Significant Bits)
{0x2D, 0x00}, // Fractional part of the PLL J.D-Divider value. (Most Significant Bits, [13:8])
{ADC_REG0_INT_CR, 0x00}, // Interrupts: Enable the Energysense Interrupt
//{ADC_REG0_PDN_CR, 0x70}, // PWRDN: Power Up, Run
{ADC_REG0_MUTE_CR, 0x00}, //DSP_CTRL; Select the decimation filter type; Disable high-pass filter; Mute Ch2(R); Mute Ch2(L); Mute Ch1(R); Mute Ch1(L)
{ADC_REG0_PGA_Val_1L, 0x08}, // PGA Value Channel 1 Left
{ADC_REG0_PGA_Val_1R, 0x08}, // PGA Value Channel 1 Right
{ADC_REG0_PGA_Val_2L, 0x08}, // PGA Value Channel 2 Left
{ADC_REG0_PGA_Val_2R, 0x08}, // PGA Value Channel 2 Right
//Page 1
//{ADC_PAGE_SEL_REG, ADC_PAGE_SEL_1},
// Page 3
//{ADC_PAGE_SEL_REG, ADC_PAGE_SEL_3},
// Page 253
//{ADC_PAGE_SEL_REG, ADC_PAGE_SEL_253},
};
All data send in PCM and verify - it`s ok, except reg 0x28 (it`s ok, bit PLL Lock Status set) and I can`t write in regs 0x01-0x04, it`s allways 0.
I also see next:
reg 0x72 - 0x03 (Stand-by)
reg 0x73 - 0x03 (32-48kHz)
reg 0x74 - 0x42 (256)
reg 0x75 - 0x00 (No errors)
reg 0x78 - 0x07 (Power OK)
No matter how I config it (Enable Auto Clock, or by table 10, or by table 13) - it`s always like this (I`m about reading reg 0x72-0x78)
May be I need something more for configuraton it?
Thanks!
