TAS2553: Non Use Pin Connection on TAS2553

Hi Sakai-san,

You should connect IVCLKIN to GND with a 10K resistor if not used.
Please make sure that you connect the feedback lines (VSENSE) as close to the speaker as possible.

Best regards,
-Ivan Salazar
Texas Instruments

Dear, Ivan-san. 

Thank you so much for your teaching & advice. 

The customer is making additional question. Please give your advice again. 

For VBAT bias, 4.5V/1A DCDC Converter is located. 

1. 47page on the TAS2553 datashhet, VBAT max current is defined. 

   Is it  a kind of peak current? 

2. If the current was insufficient, What kind of issue was concerned? 

   For instance, the output sound pressure would be decreased. ]

Best Regards, 

H. Sakai

Hi Sakai-san,

The TAS2553 will be demanding more current as the output is increasing. If the gain is increased the current will get higher.
If there is not enough current from the supply it should be protected as the device will be demanding more current.

Best regards,
-Ivan Salazar
Texas Instruments

Dear, Ivan-san. 

I would like to double-confirm your mentioning. Sorry again & again. 

I wonder "Protected"  means that TAS2553 will be shutdown by VBAT battery monitor function block

such as battery tracking AGC or VBOOST output voltage will be decreased at insufficient current from the supply? 

Best Regards, 

H. Sakai

Sakai-san,

TAS2553 will be demanding more current as the output power/gain is increased. The protection I'm talking about is on the supply stage to avoid any possible damage to this stage. TAS2553 will protect itself in case of an event.
You could setup and adjust the AGC to keep the device within the current limits.

Best regards,
-Ivan Salazar
Texas Instruments

Dear, Ivan-san.

Thank you so much for all of your teachings.

It is first time for us to use TAS2553, Please teach more although it is quite fundermental.

1. PLL : DS page 16 & 17 described PLL CLK setting.

   a) I think it to set the CLK source(MCLK, BCLK, etc) and generate internal DAC & ADC clock

       utilizing divider. I wonnder my understanding is correct?

   b) I think I-V sense is needed for Boost amp function. ADC should be utilized.

       I wonnder my understanding is correct?

   c) How much value will be reasonable as the sampling rate(? sps)?

       Smart amp function will not be used. Expected as IS2 input & Boost amp.

2. Resister 0x02 bit1.

      Smart amp function will not be used. Which setting enable/disable is correct as IVSENSE_EN?

3. Resister 0x03 bit3 ~ bit6.

      Could you please teach the correct seeting for these four bits.

4. Resister 0x07 bit0 ~ bit7.

      Could you please teach the correct seeting for these eight bits.

Best Regards,

H. Sakai

     

Hi Sakai-san,

I'll try to answer your questions, please read the information below:
1.
a) Yes, PLL and CLK settings are used to configure the clock source and dividers.
b) You can use Boost without using IVSense. The ADC is used if you will send VBoost or VBat information back to the host processor.
c) You could use 44.1ksps or 48ksps. These are commonly used sampling rates.

2.
If smart amp won't be used, you can set register 0x02 bit 1 to 0. This will disable IVSense.

3.
Register 0x03: Bit 6 can be set to 0. Bit 5 should be set to 0 if you will use digital I2S input. Bits 4-3 can be set to 11.

4.
Register 0x07 should be set to 0xFF if you won't use feedback information (smart amp).

Best regards,
-Ivan Salazar
Texas Instruments

Dear, Ivan-san.

Thank you for your teachings.

I would like to talk with you based on the customer information.
It is possible to let me know your private mail address?

Best Regards,
H. Sakai

Sakai-san,

Sure, my address is ivan.salazar@ti.com

Best regards,
-Ivan Salazar
Texas Instruments